| 2026 | FALCON-3D: Full-Chip Analytical Thermal Simulation with Lateral CONvection for 3D-Stacked ICs. | Tsung-Lin Lu, Yu-Min Lee, Pei-Yu Huang, Ching-Hsiang Wang |
| 2026 | A Collaborative Framework for Multi-Level Multi-Objective Design Space Exploration. | Jiangnan Li, Kaixiang Zhu, Yuping Bai, Yunfei Dai, Qing He, Yu He, Lingli Wang |
| 2026 | Endor: Exploit Nearly-Decode-Only Opportunities of LLM Reasoning on Near-Memory Architecture. | Jun Liu, Tianlang Zhao, Shiyi Liu, Jiancai Ye, Lin Li, Zhen Yu, Li Ding, Hao Zhou, Zhenhua Zhu, Xuefei Ning, Yuan Xie, Yu Wang, Guohao Dai |
| 2026 | PPA-driven Placement via Adaptive Cluster Constraints Optimization. | Ziyan Liu, Siyuan Xu, Jie Wang, Zijie Geng, Yeqiu Chen, Mingxuan Yuan, Jianye Hao, Feng Wu |
| 2026 | Submodular Maximization-inspired Adaptive Routing Bend Space Planning. | Siting Liu, Peng Xu, Peiyu Liao, Keren Zhu, Yibo Lin, Bei Yu |
| 2026 | Unary Positional System: Flexible Balance of Hardware Area and Performance. | Zeshi Liu, Zheng Weng, Ruijie Tan, Guangming Tang, Haihang You |
| 2026 | An IR drop-robust Mapping Method for Reliable Memristive Accelerators. | Jinpeng Liu, Shiyi Song, Bing Wu, Huan Cheng, Heng Zhou, Xueliang Wei, Wei Tong, Dan Feng |
| 2026 | MONET: A Mixture-of-Experts Accelerator with a Multicast-Optimized Two-Tier Network-on-Chip. | Siqin Liu, Maya Roediger, Avinash Karanth |
| 2026 | Focus Session: Exploring Semantic Leakage in Edge FPGA Implementations of Neural Networks. | Zhuoran Liu, Konstantina Miteloudi, Durba Chatterjee, Lejla Batina |
| 2026 | MetaSyn: A Meta-Reinforcement Learning Framework with Multimodal Circuit Representation for Adaptive Logic Synthesis. | Shukai Liu, Ruoyan Liao, Siyu Wang, Qimin Xu, Cailian Chen |
| 2026 | Boosting the Performance of Tree-Based Speculative Decoding of LLMs on FPGAs. | Tielong Liu, Gang Li, Zitao Mo, Zeyu Zhu, Minnan Pei, Jian Cheng |
| 2026 | GRAIN: A Design-Intent-Driven Analog Layout Migration Framework. | Bingyang Liu, Haoning Jiang, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, David Z. Pan, Yibo Lin |
| 2026 | A Cluster-Based Distributed Memory Architecture for CGRAs. | Shangkun Li, Cheng Tan, Zeyu Li, Jinming Ge, Jiawei Liang, Hao Yang, Linfeng Du, Jiang Xu, Wei Zhang |
| 2026 | CoMix-D: A Low-Cost, RNG-Free Decorrelator via Correlation Mixing for Stochastic Computing. | Yexian Lin, Chunyan Wu, Kuncai Zhong, Weikang Qian |
| 2026 | A Mathematical Exploration to Equivalence Checking of Quantum Circuits. | You-Cheng Lin, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Chia-Chieh Chu, Chun-Yao Wang |
| 2026 | GPU-Accelerated Efficient Transduction for Logic Optimization. | Zhuofan Lin, Shiju Lin |
| 2026 | Near-Optimal TDM Ratio Assignment for Die-Level Routing in Multi-FPGA Systems. | Jiawei Lin, Longkun Guo, Weijie Fang |
| 2026 | CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device. | Ye Lin, Chao Fang, Xiaoyong Song, Qi Wu, Anying Jiang, Yichuan Bai, Li Du |
| 2026 | Enabling Cross-Design Power Trace Prediction with GNNs for Gate-Level Netlists. | Shih-Chun Lin, Yung-Chih Chen, Bo-Hao Huang |
| 2026 | Advancing LUT-based Threshold Logic Synthesis with Enhanced Area Estimation. | Yu-Shan Lin, Yung-Chih Chen |
| 2026 | Efficient CNN Inference on Ultra-Low-Power MCUs via Saturation-Aware Convolution. | Shiming Li, Luca Mottola, Yuan Yao, Stefanos Kaxiras |
| 2026 | ACES: A Chiplet Architecture with Resource Partition and Dynamic Scheduling for Agentic LLMs. | Hongou Li, Mingxuan Li, Zhantong Zhu, Tianyu Jia |
| 2026 | Late Breaking Results: Algorithm-Hardware Co-Design of a Sparsity-Aware Dense-Sparse Scheme for DNN Accelerators. | Yueting Li, Zhen Li, Terry Tao Ye, Weisheng Zhao |
| 2026 | EDA Flow Matters: Stage-Aware Parameter Optimization of Tool Chain. | Xinheng Li, Donger Luo, Peng Xu, Ziyang Yu, Qi Sun, Tinghuan Chen, Bei Yu, Hao Geng |
| 2026 | Bridging the Power Estimation Gap: A GNN-Based Prediction Model for Approximate Logic Synthesis. | Fuxuan Li, Ao Liu, Siting Liu, Hui Wang, Jie Han, Honglan Jiang |