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Design, Automation and Test in Europe Conference

DATE

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

9,217

1995–2026

Papers per year

1995445 peak2026

DATE papers

9,217 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2019IBM's Qiskit Tool Chain: Working with and Developing for Real Quantum Computers.Robert Wille, Rod Van Meter, Yehuda Naveh
2019Protecting RISC-V Processors against Physical Attacks.Mario Werner, Robert Schilling, Thomas Unterluggauer, Stefan Mangard
2019Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation.Dennis D. Weller, Michael Hefenbrock, Mohammad Saber Golanbari, Michael Beigl, Mehdi Baradaran Tahoori
2019An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2019Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters.Lu Wang, Leilei Wang, Dejia Shang, Cheng Zhuo, Pingqiang Zhou
2019Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis.Zi Wang, Benjamin Carrin Schfer
2019Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design.Shuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin
2019High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2019Advance Virtual Channel Reservation.Boqian Wang, Zhonghai Lu
2019Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration.Sebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid
2019Guaranteed Compression Rate for Activations in CNNs using a Frequency Pruning Approach.Sebastian Vogel, Christoph Schorn, Andre Guntoro, Gerd Ascheid
2019SACHa: Self-Attestation of Configurable Hardware.Jo Vliegen, Md Masoom Rabbani, Mauro Conti, Nele Mentens
2019Advanced 3D Technologies and Architectures for 3D Smart Image Sensors.Pascal Vivet, Gilles Sicard, Laurent Millet, Stphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sbastien Thuries, Didier Lattard, Sverine Cheramy, Perrine Batude, Fabien Clermidy
2019RTL-Aware Dataflow-Driven Macro Placement.Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Marc Galceran Oms, Ferran Martorell
2019Automatic Time-Frequency Analysis of MRPs for Mind-controlled Mechatronic Devices.Daniela De Venuto, Giovanni Mezzina
2019Self-Secured Control with Anomaly Detection and Recovery in Automotive Cyber-Physical Systems.Korosh Vatanparvar, Mohammad Abdullah Al Faruque
2019Automated Circuit Approximation Method Driven by Data Distribution.Zdenek Vascek, Vojtech Mrazek, Luks Sekanina
2019Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation.Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis
2019Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.Antonio Toro-Fras, Pablo Saraza-Canflanca, Fbio Passos, Pablo Martn-Lloret, Rafael Castro-Lpez, Elisenda Roca, Javier Martn-Martnez, Rosana Rodrguez, Montserrat Nafra, Francisco V. Fernndez
2019IDF-Autoware: Integrated Development Framework for ROS-Based Self-Driving Systems Using MATLAB/Simulink.Shota Tokunaga, Yuki Horita, Yasuhiro Oda, Takuya Azumi
2019Scalable Boolean Methods in a Modern Synthesis Flow.Eleonora Testa, Luca G. Amar, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera
2019Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata.Ahmad Tarraf, Lars Hedrich
2019LoSCache: Leveraging Locality Similarity to Build Energy-Efficient GPU L2 Cache.Jingweijia Tan, Kaige Yan, Shuaiwen Leon Song, Xin Fu
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