| 2017 | Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process. | Tushar Krishna, Arya Balachandran, Siau Ben Chiah, Li Zhang, Bing Wang, Cong Wang, Kenneth Eng-Kian Lee, Jrgen Michel, Li-Shiuan Peh |
| 2017 | Mitigation of sense amplifier degradation using input switching. | Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene |
| 2017 | Adaptive weight compression for memory-efficient neural networks. | Jong Hwan Ko, Duckhwan Kim, Taesik Na, Jaeha Kung, Saibal Mukhopadhyay |
| 2017 | READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications. | Per Gunnar Kjeldsberg, Andreas Gocht, Michael Gerndt, Lubomir Riha, Joseph Schuchart, Umbreen Sabir Mian |
| 2017 | Evaluating impact of human errors on the availability of data storage systems. | Mostafa Kishani, Reza Eftekhari, Hossein Asadi |
| 2017 | Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. | Josef Kinseher, Leonhard Heis, Ilia Polian |
| 2017 | Evaluating coherence-exploiting hardware Trojan. | Minsu Kim, Sunhee Kong, Boeui Hong, Lei Xu, Weidong Shi, Taeweon Suh |
| 2017 | Synthesis of activation-parallel convolution structures for neuromorphic architectures. | Seban Kim, Jaeyong Chung |
| 2017 | A schedulability test for software migration on multicore system. | Jung-Eun Kim, Richard M. Bradford, Tarek F. Abdelzaher, Lui Sha |
| 2017 | A novel zero weight/activation-aware hardware architecture of convolutional neural network. | Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo |
| 2017 | Leveraging aging effect to improve SRAM-based true random number generators. | Saman Kiamehr, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori |
| 2017 | Leveraging access port positions to accelerate page table walk in DWM-based main memory. | Hoda Aghaei Khouzani, Pouya Fotouhi, Chengmo Yang, Guang R. Gao |
| 2017 | Novel magnetic burn-in for retention testing of STTRAM. | Mohammad Nasim Imtiaz Khan, Anirudh Srikant Iyengar, Swaroop Ghosh |
| 2017 | QX: A high-performance quantum computer simulation platform. | Nader Khammassi, Imran Ashraf, Xiang Fu, Carmen G. Almudver, Koen Bertels |
| 2017 | Design automation for obfuscated circuits with multiple viable functions. | Shahrzad Keshavarz, Christof Paar, Daniel E. Holcomb |
| 2017 | SecureCloud: Secure big data processing in untrusted clouds. | Florian Kelbert, Franz Gregor, Rafael Pires, Stefan Kpsell, Marcelo Pasin, Aurelien Havet, Valerio Schiavoni, Pascal Felber, Christof Fetzer, Peter R. Pietzuch |
| 2017 | Voltage-controlled MRAM for working memory: Perspectives and challenges. | Wang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao |
| 2017 | Programming and analysing scenario-aware dataflow on a multi-processor platform. | Reinier van Kampenhout, Sander Stuijk, Kees Goossens |
| 2017 | BASTION: Board and SoC test instrumentation for ageing and no failure found. | Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke |
| 2017 | Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305. | Bernhard Jungk, Shivam Bhasin |
| 2017 | An energy-efficient memory hierarchy for multi-issue processors. | Tiago T. Jost, Gabriel L. Nazar, Luigi Carro |
| 2017 | Reusing trace buffers to enhance cache performance. | Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi |
| 2017 | AFEC: An analytical framework for evaluating cache performance in out-of-order processors. | Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan |
| 2017 | SLoT: A supervised learning model to predict dynamic timing errors of functional units. | Xun Jiao, Yu Jiang, Abbas Rahimi, Rajesh K. Gupta |
| 2017 | Combining structural and timing errors in overclocked inexact speculative adders. | Xun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang, Christian C. Enz, Rajesh K. Gupta |