| 2017 | Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits. | Shohdy Abdelkader, Alaa ELRouby, Mohamed Dessouky |
| 2017 | Probabilistic schedulability analysis for fixed priority mixed criticality real-time systems. | Yasmina Abdeddam, Dorin Maxim |
| 2017 | A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. | Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney |
| 2017 | Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores. | Arun Subramaniyan, Semeen Rehman, Muhammad Shafique, Akash Kumar, Jrg Henkel |
| 2017 | MINIME-validator: Validating hardware with synthetic parallel testcases. | Alper Sen, Etem Deniz, Brian Kahne |
| 2016 | A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs. | Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni |
| 2016 | A synthesis-parameter tuning system for autonomous design-space exploration. | Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni |
| 2016 | Towards low overhead control flow checking using regular structured control. | Zhiqi Zhu, Joseph Callenes-Sloan |
| 2016 | FLIC: Fast, lightweight checkpointing for mobile virtualization using NVRAM. | Kan Zhong, Duo Liu, Liang Liang, Linbo Long, Yi Lin, Zili Shao |
| 2016 | Current based PUF exploiting random variations in SRAM cells. | Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia |
| 2016 | Leader: Accelerating ReRAM-based main memory by leveraging access latency discrepancy in crossbar arrays. | Hang Zhang, Nong Xiao, Fang Liu, Zhiguang Chen |
| 2016 | Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. | Sai Zhang, Naresh R. Shanbhag |
| 2016 | Sampling-based buffer insertion for post-silicon yield improvement under process variability. | Grace Li Zhang, Bing Li, Ulf Schlichtmann |
| 2016 | Multi-story power distribution networks for GPUs. | Qixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta |
| 2016 | Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead. | Zhiyong Zhang, Lei Ju, Zhiping Jia |
| 2016 | A q-gram birthmarking approach to predicting reusable hardware. | Kevin Zeng, Peter M. Athanas |
| 2016 | SEERAD: A high speed yet energy-efficient rounding-based approximate divider. | Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram |
| 2016 | Challenges of using on-chip performance monitors for process and environmental variation compensation. | Mahroo Zandrahimi, Zaid Al-Ars, Philippe Debaud, Armand Castillejo |
| 2016 | Utilizing macromodels in floating random walk based capacitance extraction. | Wenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang, Luca Daniel |
| 2016 | Exploring specialized near-memory processing for data intensive operations. | Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin |
| 2016 | Design of latches and flip-flops using emerging tunneling devices. | Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu |
| 2016 | All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. | Ta-Tung Yen, Bin Yu, Visvesh S. Sathe |
| 2016 | Sequential analysis driven reset optimization to improve power, area and routability. | Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park |
| 2016 | Activation of logic encrypted chips: Pre-test or post-test? | Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu |
| 2016 | Memory-access aware DVFS for network-on-chip in CMPs. | Yuan Yao, Zhonghai Lu |