| 2016 | Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions. | Maria A. Serrano, Alessandra Melani, Marko Bertogna, Eduardo Quiones |
| 2016 | Monitoring of MTL specifications with IBM's spiking-neuron model. | Konstantin Selyunin, Thang Nguyen, Ezio Bartocci, Dejan Nickovic, Radu Grosu |
| 2016 | Design-Reliability Flow and Advanced Models Address IC-Reliability Issues. | Mohamed Selim, Eric Jeandeau, Cyril Desclves |
| 2016 | Accelerating source-level timing simulation. | Simon Schulz, Oliver Bringmann |
| 2016 | Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware. | Stefan Scholl, Philipp Schlfer, Norbert Wehn |
| 2016 | Holistic coupled field and circuit simulation. | Wim Schoenmaker, Peter Meuris, Christian Strohm, Caren Tischendorf |
| 2016 | Lessons learned from the EU project T-CREST. | Martin Schoeberl |
| 2016 | Error resilience and energy efficiency: An LDPC decoder design study. | Philipp Schlfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek |
| 2016 | Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs. | Karsten Scheibler, Dominik Erb, Bernd Becker |
| 2016 | Formal verification of integer multipliers by combining Grbner basis with logic reduction. | Amr A. R. Sayed-Ahmed, Daniel Groe, Ulrich Khne, Mathias Soeken, Rolf Drechsler |
| 2016 | Real-time system-level implementation of a telepresence robot using an embedded GPU platform. | Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen |
| 2016 | Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. | Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy |
| 2016 | Aging-aware voltage scaling. | Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jrg Henkel |
| 2016 | A dynamically reconfigurable ECC decoder architecture. | Awais Sani, Philippe Coussy, Cyrille Chavet |
| 2016 | Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA. | Marcos Snchez-lez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha |
| 2016 | An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture. | Reza Salkhordeh, Hossein Asadi |
| 2016 | Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid. | Yusuke Sakumoto, Ittetsu Taniguchi |
| 2016 | Pareto front analog layout placement using Satisfiability Modulo Theories. | Sherif M. Saif, Mohamed Dessouky, M. Watheq El-Kharashi, Hazem M. Abbas, Salwa M. Nassar |
| 2016 | Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor. | Aryabartta Sahu |
| 2016 | Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults. | Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli |
| 2016 | MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures. | Thiago Raupp da Rosa, Thomas Mesquida, Romain Lemaire, Fabien Clermidy |
| 2016 | Efficient monitoring of loose-ordering properties for SystemC/TLM. | Yuliia Romenska, Florence Maraninchi |
| 2016 | Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point. | Dimitrios Rodopoulos, Philippe Roussel, Francky Catthoor, Yiannakis Sazeides, Dimitrios Soudris |
| 2016 | A detailed methodology to compute Soft Error Rates in advanced technologies. | Marc Riera, Ramon Canal, Jaume Abella, Antonio Gonzlez |
| 2016 | Fault-tolerant 3-D network-on-chip design using dynamic link sharing. | Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Reza Yazdani Aminabadi, Masoud Daneshtalab |