| 2021 | RTL Design Framework for Embedded Processor by using C++ Description. | Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki |
| 2021 | Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. | Youngbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun |
| 2021 | SC4MEC: Automated Implementation of A Secure Hierarchical Calculus for Mobile Edge Computing. | Jiaqi Yin, Huibiao Zhu, Yuan Fei |
| 2021 | Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. | Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing |
| 2021 | FeFET and NCFET for Future Neural Networks: Visions and Opportunities. | Mikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Jrg Henkel, Jian-Jia Chen, Hussam Amrouch |
| 2021 | GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level. | Rozhin Yasaei, Shih-Yuan Yu, Mohammad Abdullah Al Faruque |
| 2021 | M2H: Optimizing F2FS via Multi-log Delayed Writing and Modified Segment Cleaning based on Dynamically Identified Hotness. | Lihua Yang, Zhipeng Tan, Fang Wang, Shiyun Tu, Jicheng Shao |
| 2021 | HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. | Haichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu |
| 2021 | A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme. | Ferhat Yaman, Ahmet Can Mert, Erdin ztrk, Erkay Savas |
| 2021 | Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management. | Hisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike |
| 2021 | Reliability-Driven Neuromorphic Computing Systems Design. | Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen |
| 2021 | HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. | Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo |
| 2021 | Leveraging Processor Modeling and Verification for General Hardware Modules. | Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik |
| 2021 | GOMIL: Global Optimization of Multiplier by Integer Linear Programming. | Weihua Xiao, Weikang Qian, Weiqiang Liu |
| 2021 | LAP: A Lightweight Automata Processor for Pattern Matching Tasks. | Haojun Xia, Lei Gong, Chao Wang, Xianglan Chen, Xuehai Zhou |
| 2021 | SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging. | Qiulin Wu, You Zhou, Fei Wu, Ke Wang, Hao Lv, Jiguang Wan, Changsheng Xie |
| 2021 | Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. | Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui |
| 2021 | Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. | Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho |
| 2021 | Blender: A Traffic-Aware Container Placement for Containerized Data Centers. | Zhaorui Wu, Yuhui Deng, Hao Feng, Yi Zhou, Geyong Min |
| 2021 | Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. | Nils Wistoff, Moritz Schneider, Frank K. Grkaynak, Luca Benini, Gernot Heiser |
| 2021 | Towards Automatic Design and Verification for Level 3 of the European Train Control System. | Robert Wille, Tom Peham, Judith Przigoda, Nils Przigoda |
| 2021 | Visualizing Decision Diagrams for Quantum Computing (Special Session Summary). | Robert Wille, Lukas Burgholzer, Michael Artner |
| 2021 | HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. | Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele |
| 2021 | Low-Latency Asynchronous Logic Design for Inference at the Edge. | Adrian Wheeldon, Alex Yakovlev, Rishad A. Shafik, Jordan Morris |
| 2021 | Printed Stochastic Computing Neural Networks. | Dennis D. Weller, Nathaniel Bleier, Michael Hefenbrock, Jasmin Aghassi-Hagmann, Michael Beigl, Rakesh Kumar, Mehdi B. Tahoori |