| 2007 | FPGA/DSP-based Configurable Multi-Channel Counter. | Daniele Audino, Federico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti |
| 2007 | P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications. | Ismail Assayad, Sergio Yovine |
| 2007 | A Serial Logarithmic Number System ALU. | Mark G. Arnold, Panagiotis D. Vouzis |
| 2007 | Design and Implementation of a 50MHZ DXT CoProcessor. | Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi |
| 2007 | Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. | Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo |
| 2006 | Memory Generation and Power Distribution In SOC. | Qing K. Zhu |
| 2006 | Clock-Gating in FPGAs: A Novel and Comparative Evaluation. | Yan Zhang, Jussi Roivainen, Aarne Mmmel |
| 2006 | Abstract Application Modeling for System Design Space Exploration. | Waseem Muhammad, Ludovic Apvrille, Raba Ameur-Boulifa, Sophie Coudert, Renaud Pacalet |
| 2006 | Robustness in SOC Design. | Klaus Waldschmidt |
| 2006 | A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. | Ines Viskic, Rainer Dmer |
| 2006 | Novel Modulo 2 | Haridimos T. Vergos, Costas Efstathiou |
| 2006 | ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems. | Tero Vallius, Juha Rning |
| 2006 | Adaptive High-End Microprocessor for Power-Performance Efficiency. | Pedro Trancoso |
| 2006 | A Graph Based Algorithm for Data Path Optimization in Custom Processors. | Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski |
| 2006 | Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. | Rikard Thid, Ingo Sander, Axel Jantsch |
| 2006 | Adapting EPIC Architecture's Register Stack for Virtual Stack Machines. | Jamel Tayeb, Smal Niar |
| 2006 | New Directions in Mobile Device Architectures. | Risto Suoranta |
| 2006 | Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication. | Sander Stuijk, Twan Basten, Marc Geilen, Amir Hossein Ghamarian, Bart D. Theelen |
| 2006 | A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. | Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Spars, Johnny Halkjr Pedersen |
| 2006 | Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems. | Kyriakos Stavrou, Pedro Trancoso |
| 2006 | Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. | Martin Stva, Ondrej Novk |
| 2006 | Digital RF. | Roman Staszewski |
| 2006 | Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis. | Adam Smyk, Marek S. Tudruj |
| 2006 | Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor Networks. | Juan A. Snchez, Pedro M. Ruiz |
| 2006 | VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. | Armando Snchez-Pea, Pedro P. Carballo, Luz Garca, Antonio Nez |