| 2004 | Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design. | Cao Cao, Bengt Oelmann |
| 2004 | Cost-Efficient Implementation of Adaptive Finite State Machines. | Maik Boden, Manfred Koegst, Jos Luis Tiburcio Bada, Steffen Rlke |
| 2004 | An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. | Ivan Blunno, Guy Alain Narboni, Claudio Passerone |
| 2004 | A Simple Micro-Threaded Data-Driven Processor. | Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland |
| 2004 | A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines. | Chris Bailey |
| 2004 | Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. | Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam |
| 2004 | A Threshold Logic Synthesis Tool for RTD Circuits. | Maria J. Avedillo, Jos M. Quintana |
| 2004 | Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder. | Imed Aouadi, Omar Hammami |
| 2004 | Scene Management Models and Overlap Tests for Tile-Based Rendering. | Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha |
| 2004 | A Mechanism for Implementing Precise Exceptions in Pipelined Processors. | Soyeb Alli, Chris Bailey |
| 2004 | Compiler-Directed Dynamic Memory Disambiguation for Loop Structures. | Soyeb Alli, Chris Bailey |
| 2004 | Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. | Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi |
| 2003 | Multi Component Digital Circuit Optimization by Solving FSM Equations. | Nina Yevtushenko, Svetlana Zharikova, Maria Vetrova |
| 2003 | Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. | Hiroto Yasuura |
| 2003 | Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration. | Armin Wellig, Julien Zory |
| 2003 | A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. | Ling Wang, Henry Selvaraj |
| 2003 | Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm. | Filip Traugott, Kim Andersson, Andreas Lfgren, Lennart Lindh |
| 2003 | Variations on Truncated Multiplication. | James E. Stine, Oliver M. Duverne |
| 2003 | DYNORA: A New Caching Technique. | P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran |
| 2003 | T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors. | Sandro Neves Soares, Flvio Rech Wagner |
| 2003 | A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. | Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, Antnio de Brito Ferrari |
| 2003 | Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. | Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida |
| 2003 | Hierarchical Constraint Conscious RT-level Test Generation. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | Causality Constraints for Processor Architectures with Sub-Word Parallelism. | Rainer Schaffer, Renate Merker, Francky Catthoor |
| 2003 | Testable Design Verification Using Petri Nets. | Richard Ruzicka |