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Forum on Specification and Design Languages

FDL

C

CORE rank

CORE rank (raw)

C

Fields of research

Software Engineering

Papers indexed

774

2003–2025

Papers per year

200371 peak2025

FDL papers

774 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2016IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models.Sara Vinco, Michele Lora, Enrico Macii, Massimo Poncino
2016Heterogeneous computing with accelerators: an overview with examples.Ana Lucia Varbanescu, Jie Shen
2016Equivalence checking on ESL utilizing a priori knowledge.Niels Thole, Heinz Riener, Grschwin Fey
2016Fault-effect analysis on system-level hardware modeling using virtual prototypes.Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
2016Using event-B and Modelica to evaluate thermal management strategies in many core systems.Colin F. Snook, Tom J. Kazmierski
2016Compositional specification of functionality and timing of manufacturing systems.Bram van der Sanden, Joo Bastos, Jeroen Voeten, Marc Geilen, Michel A. Reniers, Twan Basten, Johan Jacobs, Ramon R. H. Schiffelers
2016Automated synthesis of cyber-physical systems from joint controller/architecture specifications.Debayan Roy, Licong Zhang, Wanli Chang, Samarjit Chakraborty
2016Change impact analysis for hardware designs from natural language to system level.Martin Ring, Jannis Stoppe, Christoph Lth, Rolf Drechsler
2016Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems.Ashur Rafiev, Fei Xia, Alexei Iliasov, Rem Gensh, Ali Aalsaud, Alexander B. Romanovsky, Alexandre Yakovlev
2016Toolchain integration of runtime variability and aging awareness in multicore platforms.Ramakrishna Venkata Nittala, Francesco Barchi, Gianvito Urgese, Andrea Acquaviva
2016Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation.Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau, Mathieu Jan, Hela Guesmi
2016Error-free near-threshold adiabatic CMOS logic in presence of process variation.Yue Lu, Tom J. Kazmierski
2016A modular design space exploration framework for multiprocessor real-time systems.Nima Khalilzad, Kathrin Rosvall, Ingo Sander
2016On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler
2016Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients.Ghaith Bany Hamad, Ghaith Kazma, Otmane At Mohamed, Yvon Savaria
2016Feature based state space coverage of analog circuits.Andreas Furtig, Sebastian Steinhorst, Lars Hedrich
2016Cascading metamodels from different sources for performance analysis of a power module.Christine Forster, Stefan Buschhorn, Monica Rafaila, Linus Maurer, Georg Pelz
2016Automatic generation of self-adaptive transactors from PSL assertions.Florenc Demrozi, Graziano Pravadelli, Francesco Stefanni
2016Building product-lines of mixed-criticality systems.Simon Barner, Alexander Diewald, Fernando Eizaguirre, Anatoly Vasilevskiy, Franck Chauvel
2016Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking.Marwan Ammar, Ghaith Bany Hamad, Otmane At Mohamed, Yvon Savaria
2016Designing reliable cyber-physical systems overview associated to the special session at FDL'16.Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Grschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Knighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Rck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2015Conservative behavioural modelling in systemc-AMS.Sara Vinco, Michele Lora, Mark Zwolinski
2015Architectural system modeling for correct-by-construction RTL design.Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2015Towards a toolchain for assertion-driven test sequence generation.Laurence Pierre
2015Modeling power consumption at system-level for design of power integrity-aware AMS-circuits.Xiao Pan, Javier Moreno Molina, Christoph Grimm
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