| 2018 | Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore. | Jean-Louis Colao, Bruno Pagano, Cdric Pasteur, Marc Pouzet |
| 2018 | SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation. | Zhongqi Cheng, Tim Schmidt, Rainer Dmer |
| 2018 | Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests. | Martial Chabot, Laurence Pierre, Alexandre Nabais-Moreno |
| 2018 | Transaction-level Functional Mockup Units for Cyber-Physical Virtual Platforms. | Stefano Centomo, Michele Lora, Franco Fummi |
| 2017 | Runtime task mapping for lifetime budgeting in many-core systems. | Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak |
| 2017 | Asil decomposition using SMT. | Mona Safar |
| 2017 | Language and Hardware Acceleration Backend for Graph Processing. | Andrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew D. Brown |
| 2017 | Language and hardware acceleration backend for graph processing. | Andrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew D. Brown |
| 2017 | A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
| 2017 | Towards consistency checking between HDL and UPF descriptions. | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
| 2017 | Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | Real-time ticks for synchronous programming. | Reinhard von Hanxleden, Timothy Bourke, Alain Girault |
| 2017 | Actor fission transformations for executing dataflow programs on manycores. | Essayas Gebrewahid, Zain Ul-Abdin |
| 2017 | Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction. | Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski |
| 2017 | Fault analysis in analog circuits through language manipulation and abstraction. | Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski |
| 2017 | Rethinking of I/O-automata composition. | Sarah Chabane, Raba Ameur-Boulifa, Mohamed Mezghiche |
| 2017 | Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces. | Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi |
| 2017 | Automatic generation of cycle-accurate Simulink blocks from hdl ips. | Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi |
| 2017 | Symbolic Simulation of Dataflow Synchronous Programs with Timers. | Guillaume Baudart, Timothy Bourke, Marc Pouzet |
| 2017 | Symbolic simulation of dataflow synchronous programs with timers. | Guillaume Baudart, Timothy Bourke, Marc Pouzet |
| 2017 | Identifying bottlenecks in manufacturing systems using stochastic criticality analysis. | Joo Bastos, Bram van der Sanden, Olaf Donk, Jeroen Voeten, Sander Stuijk, Ramon R. H. Schiffelers, Henk Corporaal |
| 2017 | Compositional timing-aware semantics for synchronous programming. | Joaqun Aguado, Michael Mendler, Jia Jie Wang, Bruno Bodin, Partha S. Roop |
| 2016 | Flexible runtime verification based on logical clock constraints. | Daian Yue, Vania Joloboff, Frdric Mallet |
| 2016 | Maintenance of specification models in industry using Edapt. | Y. Vissers, J. G. M. Mengerink, Ramon R. H. Schiffelers, Alexander Serebrenik, Michel A. Reniers |