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International Symposium on High Performance Computer Architecture

HPCA

A*

CORE rank

CORE rank (raw)

A*

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software

Papers indexed

1,671

1995–2026

Papers per year

1995122 peak2026

HPCA papers

1,671 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2011Cuckoo directory: A scalable directory for many-core systems.Michael Ferdman, Pejman Lotfi-Kamran, Ken Balet, Babak Falsafi
2011CHIPPER: A low-complexity bufferless deflection router.Chris Fallin, Chris Craik, Onur Mutlu
2011Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing.Feng Chen, Rubao Lee, Xiaodong Zhang
2011Hardware/software-based diagnosis of load-store queues using expandable activity logs.Javier Carretero, Xavier Vera, Jaume Abella, Tanaus Ramrez, Matteo Monchiero, Antonio Gonzlez
2011Fast thread migration via cache working set prediction.Jeffery A. Brown, Leo Porter, Dean M. Tullsen
2011Safe and efficient supervised memory systems.Jayaram Bobba, Marc Lupon, Mark D. Hill, David A. Wood
2011Bloom Filter Guided Transaction Scheduling.Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2011Shared last-level TLBs for chip multiprocessors.Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi
2011Archipelago: A polymorphic cache design for enabling robust near-threshold operation.Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
2011Checked Load: Architectural support for JavaScript type-checking on mobile processors.Owen Anderson, Emily Fortuna, Luis Ceze, Susan J. Eggers
2010Simple virtual channel allocation for high throughput and high frequency on-chip routers.Yi Xu, Bo Zhao, Youtao Zhang, Jun Yang
2010Handling branches in TLS systems with Multi-Path Execution.Polychronis Xekalakis, Marcelo Cintra
2010An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee
2010Architecting for power management: The IBM POWER7Malcolm S. Ware, Karthick Rajamani, Michael S. Floyd, Bishop Brock, Juan C. Rubio, Freeman L. Rawson III, John B. Carter
2010DMA++: on the fly data realignment for on-chip memories.Nikola Vujic, Marc Gonzlez, Felipe Cabarcas, Alex Ramrez, Xavier Martorell, Eduard Ayguad
2010Worth their watts? - an empirical study of datacenter servers.Arunchandar Vasan, Anand Sivasubramaniam, Vikrant Shimpi, T. Sivabalan, Rajesh Subbiah
2010Towards scalable, energy-efficient, bus-based on-chip networks.Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
2010Extreme scale computing: Challenges and opportunities.Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun
2010DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance.Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen
2010A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li
2010UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy
2010Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing.Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montao
2010FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar.Yan Pan, John Kim, Gokhan Memik
2010Graphite: A distributed parallel simulator for multicores.Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald III, Nathan Beckmann, Christopher Celio, Jonathan Eastep, Anant Agarwal
2010ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture.Javier Merino, Valentin Puente, Jos-ngel Gregorio
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