| 2010 | Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance. | Fang Liu, Xiaowei Jiang, Yan Solihin |
| 2010 | Operating system support for overlapping-ISA heterogeneous multi-core architectures. | Tong Li, Paul Brett, Rob C. Knauerhase, David A. Koufaty, Dheeraj Reddy, Scott Hahn |
| 2010 | COMIC++: A software SVM system for heterogeneous multicore accelerator clusters. | Jaejin Lee, Jun Lee, Sangmin Seo, Jungwon Kim, Seungkyun Kim, Zehra Sura |
| 2010 | StimulusCache: Boosting performance of chip multiprocessors with excess cache. | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
| 2010 | Application performance modeling in a virtualized environment. | Sajib Kundu, Raju Rangaswami, Kaushik Dutta, Ming Zhao |
| 2010 | ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. | Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter |
| 2010 | A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems. | Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John |
| 2010 | Designing a processor from the ground up to allow voltage/reliability tradeoffs. | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2010 | CHOP: Adaptive filter-based DRAM caching for CMP server platforms. | Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian |
| 2010 | LiteTM: Reducing transactional state overhead. | Syed Ali Raza Jafri, Mithuna Thottethodi, T. N. Vijaykumar |
| 2010 | SIF: Overcoming the limitations of SIMD devices via implicit permutation. | Libo Huang, Li Shen, Zhiying Wang, Wei Shi, Nong Xiao, Sheng Ma |
| 2010 | BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution. | Andrew D. Hilton, Amir Roth |
| 2010 | LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. | Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas |
| 2010 | Interval simulation: Raising the level of abstraction in architectural simulation. | Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout |
| 2010 | Value Based BTB Indexing for indirect jump prediction. | Muhammad Umar Farooq, Lei Chen, Lizy Kurian John |
| 2010 | HARE: Hardware assisted reverse execution. | Ioannis Doudalis, Milos Prvulovic |
| 2010 | High performance network virtualization with SR-IOV. | Yaozu Dong, Xiaowei Yang, Xiaoyong Li, Jianhui Li, Kun Tian, Haibing Guan |
| 2010 | Scalable architectural support for trusted software. | David Champagne, Ruby B. Lee |
| 2010 | Explaining cache SER anomaly using DUE AVF measurement. | Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert |
| 2010 | Delay-Hiding energy management mechanisms for DRAM. | Mingsong Bi, Ran Duan, Chris Gniady |
| 2010 | IADVS: On-demand performance for interactive applications. | Mingsong Bi, Igor Crk, Chris Gniady |
| 2010 | Is hardware innovation over? | Arvind |
| 2010 | Exascale computing: The challenges and opportunities in the next decade. | Tilak Agerwala |
| 2010 | High-Performance low-vcc in-order core. | Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio Gonzlez |
| 2009 | Reconciling specialization and flexibility through compound circuits. | Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam |