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International Symposium on High Performance Computer Architecture

HPCA

A*

CORE rank

CORE rank (raw)

A*

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software

Papers indexed

1,671

1995–2026

Papers per year

1995122 peak2026

HPCA papers

1,671 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009A low-radix and low-diameter 3D interconnection network design.Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang
2009Practical off-chip meta-data for temporal memory streaming.Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos
2009A novel architecture of the 3D stacked MRAM L2 cache for CMPs.Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen
2009Criticality-based optimizations for efficient load processing.Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh
2009Lightweight predication support for out of order processors.Mark Stephenson, Lixin Zhang, Ram Rangan
2009Eliminating microarchitectural dependency from Architectural Vulnerability.Vilas Sridharan, David R. Kaeli
2009Design and implementation of software-managed caches for multicores with local memory.Sangmin Seo, Jaejin Lee, Zehra Sura
2009Voltage emergency prediction: Using signatures to reduce operating margins.Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David M. Brooks
2009Industrial perspectives panel.Parthasarathy Ranganathan
2009Adaptive Spill-Receive for robust high-performance caching in CMPs.Moinuddin K. Qureshi
2009CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit Riaz Sheikh, Shrirang M. Yardi
2009Multi-core demands multi-interfaces.Yale N. Patt
2009Architectural Contesting.Hashem Hashemi Najaf-abadi, Eric Rotenberg
2009Elastic-buffer flow control for on-chip networks.George Michelogiannakis, James D. Balfour, William J. Dally
2009Prediction router: Yet another low latency on-chip router architecture.Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2009Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell
2009Accurate microarchitecture-level fault modeling for studying hardware faults.Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve
2009Characterization of Direct Cache Access on multi-core systems and 10GbE.Amit Kumar, Ram Huggahalli, Srihari Makineni
2009Hardware-software integrated approaches to defend against software cache-based side channel attacks.Jingfei Kong, Onur Aciimez, Jean-Pierre Seifert, Huiyang Zhou
2009Feedback mechanisms for improving probabilistic memory prefetching.Ibrahim Hur, Calvin Lin
2009iCFP: Tolerating all-level cache misses in in-order processors.Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
2009Opportunities beyond single-core microprocessors.Mark D. Hill
2009Variation-aware dynamic voltage/frequency scaling.Sebastian Herbert, Diana Marculescu
2009Express Cube Topologies for on-Chip Interconnects.Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
2009Blueshift: Designing processors for timing speculation from the ground up.Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles
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