| 1989 | Computation with simultaneously concurrent error detection using bi-directional operands. | L. G. Chen, T. H. Chen |
| 1989 | A systolic approach to multistage interconnection network design. | Chung-Han Chen, Laxmi N. Bhuyan |
| 1989 | A module-sliced approach for high yield VLSI/WSI processors. | Yi-Chieh Chang, Kang G. Shin |
| 1989 | Magnitude classes in switch-level modeling. | Eduard Cerny, John P. Hayes, Nicholas C. Rumin |
| 1989 | Fault-tolerant VLSI processor array for the SVD. | Joseph R. Cavallaro, Christopher D. Near, M. mit Uyar |
| 1989 | A system simulation environment within Digital. | Quinn Canfield, Paul Barford, Paul Kinzelman, Cary Trlica |
| 1989 | Modeling timing assumptions with trace theory. | Jerry R. Burch |
| 1989 | An algorithm for voice and data integration on packet-switched local area networks. | Christopher Bucci, Alexander Albicki |
| 1989 | Internal ECL-BiCMOS translator circuits in half micron technology. | Gerard Boudon, Frank Wallart, Eric Maillart |
| 1989 | Verifying pipelined hardware using symbolic logic simulation. | Soumitra Bose, Allan L. Fisher |
| 1989 | A VLSI residue arithmetic multiplier with fault detection capability. | V. Bobin, D. Radhakrishnan |
| 1989 | Frigg: a simulation environment for multiple-processor DSP system development. | Jeffrey C. Bier, Edward A. Lee |
| 1989 | Ordered binary decision diagrams and circuit structure. | C. Leonard Berman |
| 1989 | Testability of digital circuits via the spectral domain. | Brian R. Bannister, David R. Melton, Gaynor E. Taylor |
| 1989 | IBM second-generation RISC machine organization. | H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan |
| 1989 | Novel architecture for a high performance full custom graphics processor. | M. D. Asal, J. D. Keay, A. M. Fellows, I. C. Robertson, N. K. Ing-Simmons, I. J. Sherlock |
| 1989 | Floorplan optimization on multiprocessors. | Sunil Arvindam, Vipin Kumar, V. Nageshwara Rao |
| 1989 | System-level design verification in the AT&T Computer Division: tools. | Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon |
| 1989 | System-level design verification in the AT&T computer division: overview and strategy. | Miron Abramovici, J. W. Bierbauer, R. H. Hellman, C. L. Hong, David T. Miller, R. G. Taylor |
| 1988 | A matched-delay CMOS TDM multiplexer cell. | Charles A. Zukowski, Kevin Shum |
| 1988 | Variable reduction in MOS timing models. | Charles A. Zukowski, De-Ping Chen |
| 1988 | Interconnection delay in very high-speed VLSI. | D. Zhou, Franco P. Preparata, S. M. Kang |
| 1988 | Computer-aided simulation of optical interconnects for high-speed digital systems. | Andrew T. Yang, D. S. Gao, S. M. Kang |
| 1988 | HIT: a standard constructional system for testability and maintainability. | Brian R. Wilkins |
| 1988 | A proposed standard test bus and boundary scan architecture. | Lee Whetsel |