Robert K. Brayton
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
223
Venues
19
Active years
1988–2021
Best venue rank
A*
Where they publish
Papers
223 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | DAC | Deep Integration of Circuit Simulator and SAT Solver. | He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amar, Alan Mishchenko, Robert K. Brayton |
| 2018 | ASPDAC | SAT-based area recovery in structural technology mapping. | Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton |
| 2018 | DAC | Efficient computation of ECO patch functions. | Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton |
| 2018 | DAC | Canonical computation without canonical representation. | Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amar, Antun Domic |
| 2018 | DATE | Improvements to boolean resynthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2018 | DATE | Practical exact synthesis. | Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amar, Robert K. Brayton, Giovanni De Micheli |
| 2017 | ASPDAC | Fast-extract with cube hashing. | Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, Andr Incio Reis |
| 2017 | FMCAD | Property directed reachability with word-level abstraction. | Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton |
| 2017 | ICCAD | Enabling exact delay synthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2016 | FMCAD | Efficient uninterpreted function abstraction and refinement for word-level model checking. | Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton |
| 2016 | ICCAD | Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. | Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
| 2016 | SAT | 2QBF: Challenges and Solutions. | Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton |
| 2016 | SAT | Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. | Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli |
| 2015 | DAC | Sequential equivalence checking of clock-gated circuits. | Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton |
| 2015 | DSD | Bi-Decomposition Using Boolean Relations. | Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa |
| 2015 | FMCAD | Simulation Graphs for Reverse Engineering. | Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton |
| 2015 | FPGA | Technology Mapping into General Programmable Cells. | Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene |
| 2015 | SEFM | Automated Synthesis of Protocol Converters with BALM-II. | Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko |
| 2014 | ASPDAC | ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. | Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury |
| 2013 | DATE | GLA: gate-level abstraction revisited. | Alan Mishchenko, Niklas En, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla |
| 2013 | DATE | A semi-canonical form for sequential AIGs. | Alan Mishchenko, Niklas En, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma |
| 2013 | FMCAD | LEC: Learning Driven Data-path Equivalence Checking. | Jiang Long, Robert K. Brayton, Michael L. Case |
| 2013 | MEMOCODE | Ranking structure in communication fabrics. | Sayak Ray, Robert K. Brayton |
| 2012 | DATE | Scalable progress verification in credit-based flow-control systems. | Sayak Ray, Robert K. Brayton |
| 2012 | DATE | Mapping into LUT structures. | Sayak Ray, Alan Mishchenko, Niklas En, Robert K. Brayton, Stephen Jang, Chao Chen |
| 2011 | FMCAD | Efficient implementation of property directed reachability. | Niklas En, Alan Mishchenko, Robert K. Brayton |
| 2011 | FMCAD | Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
| 2011 | ICCAD | Delay optimization using SOP balancing. | Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets |
| 2010 | CAV | ABC: An Academic Industrial-Strength Verification Tool. | Robert K. Brayton, Alan Mishchenko |
| 2010 | FMCAD | Combinational techniques for sequential equivalence checking. | Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton |
| 2010 | FPGA | Global delay optimization using structural choices. | Alan Mishchenko, Robert K. Brayton, Stephen Jang |
| 2009 | DATE | Speculative reduction-based scalable redundancy identification. | Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton |
| 2009 | DATE | Sequential logic rectifications with approximate SPFDs. | Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith |
| 2009 | FPGA | SmartOpt: an industrial strength framework for logic synthesis. | Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton |
| 2009 | FPGA | Scalable don't-care-based logic optimization and resynthesis. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |
| 2008 | DAC | Merging nodes under sequential observability. | Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton |
| 2008 | DAC | Scalable min-register retiming under timing and initializability constraints. | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
| 2008 | FMCAD | Invariant-Strengthened Elimination of Dependent State Elements. | Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony |
| 2008 | FMCAD | Recording Synthesis History for Sequential Verification. | Alan Mishchenko, Robert K. Brayton |
| 2008 | ICCAD | Boolean factoring and decomposition of logic networks. | Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee |
| 2008 | ICCAD | Scalable and scalably-verifiable sequential synthesis. | Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang |
| 2008 | ICCAD | Placement based multiplier rewiring for cell-based designs. | Fan Mo, Robert K. Brayton |
| 2007 | ASPDAC | Automating Logic Rectification by Approximate SPFDs. | Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton |
| 2007 | DAC | On Resolution Proofs for Combinational Equivalence. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann |
| 2007 | FMCAD | Automated Extraction of Inductive Invariants to Aid Model Checking. | Michael L. Case, Alan Mishchenko, Robert K. Brayton |
| 2007 | FMCAD | Fast Minimum-Register Retiming via Binary Maximum-Flow. | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
| 2007 | ICCAD | Combinational and sequential mapping with priority cuts. | Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton |
| 2007 | ICCAD | A simultaneous bus orientation and bused pin flipping algorithm. | Fan Mo, Robert K. Brayton |
| 2006 | DAC | DAG-aware AIG rewriting a fresh look at combinational logic synthesis. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
| 2006 | DAC | Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. | Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske |
| 2006 | FPGA | Improvements to technology mapping for LUT-based FPGAs. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
| 2006 | ICCAD | Factor cuts. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton |
| 2006 | ICCAD | Improvements to combinational equivalence checking. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas En |
| 2005 | DATE | SAT-Based Complete Don't-Care Computation for Network Optimization. | Alan Mishchenko, Robert K. Brayton |
| 2005 | DATE | Efficient Solution of Language Equations Using Partitioned Representations. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko |
| 2005 | ICCAD | Reducing structural bias in technology mapping. | Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam |
| 2005 | ICCAD | Synthesis methodology for built-in at-speed testing. | Yinghua Li, Alex Kondratyev, Robert K. Brayton |
| 2004 | CAV | Functional Dependency for Verification Reduction. | Jie-Hong Roland Jiang, Robert K. Brayton |
| 2004 | DAC | A timing-driven module-based chip design flow. | Fan Mo, Robert K. Brayton |
| 2004 | ICCAD | A new incremental placement algorithm and its application to congestion-aware divisor extraction. | Satrajit Chatterjee, Robert K. Brayton |
| 2004 | ICCAD | On breakable cyclic definitions. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 2003 | ASPDAC | Don't cares in logic minimization of extended finite state machines. | Yunjian Jiang, Robert K. Brayton |
| 2003 | DAC | Generalized cofactoring for logic function evaluation. | Yunjian Jiang, Slobodan Matic, Robert K. Brayton |
| 2003 | DATE | Reducing Multi-Valued Algebraic Operations to Binary. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 2003 | DATE | Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. | Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli |
| 2003 | ICCAD | A Theory of Non-Deterministic Networks. | Alan Mishchenko, Robert K. Brayton |
| 2002 | DAC | Software synthesis from synchronous specifications using logic simulation techniques. | Yunjian Jiang, Robert K. Brayton |
| 2002 | DAC | River PLAs: a regular circuit structure. | Fan Mo, Robert K. Brayton |
| 2002 | DATE | Using Problem Symmetry in Search Based Satisfiability Algorithms. | Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton |
| 2002 | ICCAD | Simplification of non-deterministic multi-valued networks. | Alan Mishchenko, Robert K. Brayton |
| 2002 | ICCAD | Whirlpool PLAs: a regular logic structure and their synthesis. | Fan Mo, Robert K. Brayton |
| 2002 | ICCAD | Topologically constrained logic synthesis. | Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton |
| 2001 | DATE | Using SAT for combinational equivalence checking. | Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton |
| 2001 | ICCAD | Compatible Observability Don't Cares Revisited. | Robert K. Brayton |
| 2001 | ICCAD | A Force-Directed Maze Router. | Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2001 | ICCAD | Sequential SPFDs. | Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton |
| 2001 | ICCAD | Solution of Parallel Language Equations for Logic Synthesis. | Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli |
| 2001 | ICCD | A Timing-Driven Macro-Cell Placement Algorithm. | Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2000 | DAC | Area and search space control for technology mapping. | Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten |
| 2000 | ICCAD | Don't Cares and Multi-Valued Logic Network Minimization. | Yunjian Jiang, Robert K. Brayton |
| 2000 | ICCAD | Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. | Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 2000 | ICCAD | A Force-Directed Macro-Cell Placer. | Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2000 | ICCD | Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. | Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1999 | DAC | A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. | Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli |
| 1999 | DAC | Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. | Abdallah Tabbara, Robert K. Brayton, A. Richard Newton |
| 1999 | DATE | Using Combinational Verification for Sequential Circuits. | Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton |
| 1999 | ICCAD | Probabilistic state space search. | Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton |
| 1999 | ICCAD | Timing-safe false path removal for combinational modules. | Yuji Kukimoto, Robert K. Brayton |
| 1999 | VLSID | Multi-Valued Logic Synthesis. | Robert K. Brayton, Sunil P. Khatri |
| 1999 | VLSID | Sequential Multi-Valued Network Simplification using Redundancy Removal. | Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1998 | CAV | Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. | Adrian J. Isles, Ramin Hojati, Robert K. Brayton |
| 1998 | CAV | Structural Symmetry and Model Checking. | Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton |
| 1998 | DAC | Hierarchical Functional Timing Analysis. | Yuji Kukimoto, Robert K. Brayton |
| 1998 | DAC | Delay-Optimal Technology Mapping by DAG Covering. | Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar |
| 1998 | DAC | Planning for Performance. | Ralph H. J. M. Otten, Robert K. Brayton |
| 1998 | DATE | Combinational Verification based on High-Level Functional Specifications. | Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton |
| 1998 | ICCAD | Wireplanning in logic synthesis. | Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1998 | ICCAD | On the optimization power of retiming and resynthesis transformations. | Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton |
| 1998 | ICCAD | Implementation and use of SPFDs in optimizing Boolean networks. | Subarnarekha Sinha, Robert K. Brayton |
| 1998 | VLSID | Efficient Verification and Synthesis using Design Commonalities. | Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton |
| 1997 | CAV | Partial-Order Reduction in Symbolic State Space Exploration. | Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani |
| 1997 | CAV | STARI: A Case Study in Compositional and Hierarchical Timing Verification. | Serdar Tasiran, Robert K. Brayton |
| 1997 | DAC | Exact Required Time Analysis via False Path Detection. | Yuji Kukimoto, Robert K. Brayton |
| 1997 | ICCAD | Negative thinking by incremental problem solving: application to unate covering. | Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ICCAD | A fast and robust exact algorithm for face embedding. | Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ICCAD | Approximate timing analysis of combinational circuits under the XBD0 model. | Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton |
| 1997 | ICCAD | Sequential optimisation without state space exploration. | Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ICCAD | Reachability analysis using partitioned-ROBDDs. | Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ICCD | Timed Binary Decision Diagrams. | Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton |
| 1997 | ICCD | Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. | Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1997 | ITC | Efficient Identification of Non-Robustly Untestable Path Delay Faults. | Zhongcheng Li, Robert K. Brayton, Yinghua Min |
| 1996 | CAV | Verifying Continuous Time Markov Chains. | Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton |
| 1996 | CAV | VIS: A System for Verification and Synthesis. | Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa |
| 1996 | CONCUR | Verifying Abstractions of Timed Systems. | Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton |
| 1996 | DAC | Engineering Change in a Non-Deterministic FSM Setting. | Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | DAC | High Performance BDD Package By Exploiting Memory Hiercharchy. | Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | FMCAD | VIS. | Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa |
| 1996 | FMCAD | Verification Using Uninterpreted Functions and Finite Instantiations. | Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton |
| 1996 | FMCAD | Decomposition Techniques for Efficient ROBDD Construction. | Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita |
| 1996 | ICCAD | The case for retiming with explicit reset circuitry. | Vigyan Singhal, Sharad Malik, Robert K. Brayton |
| 1996 | ICCD | Early Quantification and Partitioned Transition Relations. | Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton |
| 1996 | ICCD | Latch Redundancy Removal Without Global Reset. | Shaz Qadeer, Robert K. Brayton, Vigyan Singhal |
| 1996 | ICCD | Binary decision diagrams on network of workstation. | Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1996 | VLSID | A study of composition schemes for mixed apply/compose based construction of ROBDDs. | Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | CAV | Supervisory Control of Finite State Machines. | Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha |
| 1995 | CAV | Automatic Datapath Abstraction In Hardware Systems. | Ramin Hojati, Robert K. Brayton |
| 1995 | CAV | The Rabin Index and Chain Automata, with Applications to Automatas and Games. | Sriram C. Krishnan, Anuj Puri, Robert K. Brayton, Pravin Varaiya |
| 1995 | DAC | The Validity of Retiming Sequential Circuits. | Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton |
| 1995 | DATE | Decomposition of logic functions for minimum transition activity. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | ICCAD | Sequential synthesis using S1S. | Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | ICCAD | Multi-level logic optimization of FSM networks. | Huey-Yih Wang, Robert K. Brayton |
| 1995 | ICCD | Implicit state minimization of non-deterministic FSMs. | Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | ICCD | Incremental methods for FSM traversal. | Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal |
| 1995 | ISCAS | Power-Up Delay for Retiming Digital Circuits. | Vigyan Singhal, Robert K. Brayton, Carl Pixley |
| 1995 | VLSID | Functional clock schedule optimization. | Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | STACS | Structural Complexity of Omega-Automata. | Sriram C. Krishnan, Anuj Puri, Robert K. Brayton |
| 1994 | CAV | Improving Language Containment Using Fairness Graphs. | Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton |
| 1994 | CAV | Criteria for the Simple Path Property in Timed Automata. | William K. C. Lam, Robert K. Brayton |
| 1994 | DAC | HSIS: A BDD-Based Environment for Formal Verification. | Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | BDD Variable Ordering for Interacting Finite State Machines. | Adnan Aziz, Serdar Tasiran, Robert K. Brayton |
| 1994 | DAC | A Fully Implicit Algorithm for Exact State Minimization. | Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | Exact Minimum Cycle Times for Finite State Machines. | William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | Optimum Functional Decomposition Using Encoding. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | Performance Optimization Using Exact Sensitization. | Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | DAC | Heuristic Minimization of BDDs Using Don't Cares. | Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton |
| 1994 | DAC | Permissible Observability Relations in FSM Networks. | Huey-Yih Wang, Robert K. Brayton |
| 1994 | ICALP | Equivalences for Fair Kripke Structures. | Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1994 | ICCAD | A redesign technique for combinational circuits based on gate reconnections. | Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton |
| 1994 | ICCAD | Multi-level synthesis for safe replaceability. | Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton |
| 1994 | ICCAD | Incremental formal design verification. | Gitanjali Swamy, Robert K. Brayton |
| 1994 | ICCD | Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. | Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton |
| 1994 | ICCD | An Exact Optimization of Two-Level Acyclic Sequential Circuits. | Ellen Sentovich, Robert K. Brayton |
| 1994 | ISAAC | Deterministic w Automata vis-a-vis Deterministic Buchi Automata. | Sriram C. Krishnan, Anuj Puri, Robert K. Brayton |
| 1993 | CAV | Logic Synthesis and Design Verification. | Robert K. Brayton |
| 1993 | CAV | BDD-Based Debugging Of Design Using Language Containment and Fair CTL. | Ramin Hojati, Robert K. Brayton, Robert P. Kurshan |
| 1993 | CAV | Alternating RQ Timed Automata. | William K. C. Lam, Robert K. Brayton |
| 1993 | DAC | A Unified Approach to Language Containment and Fair CTL Model Checking. | Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan |
| 1993 | DAC | Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. | William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | DAC | Delay Fault Coverage and Performance Tradeoffs. | William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | DAC | On Computing the Transitive Closure of a State Transition Relation. | Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton |
| 1993 | DAC | Espresso-Signature: A New Exact Minimizer for Logic Functions. | Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | DAC | Elimination of Dynamic hazards by Factoring. | Cho W. Moon, Robert K. Brayton |
| 1993 | DAC | Sequential Synthesis for Table Look Up Programmable Gate Arrays. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | DAC | Resynthesis of Multi-Phase Pipelines. | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCAD | Cube-packing and two-level minimization. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCAD | Minimum padding to satisfy short path constraints. | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCAD | Input don't care sequences in FSM networks. | Huey-Yih Wang, Robert K. Brayton |
| 1993 | ICCAD | The maximum set of permissible behaviors for FSM networks. | Yosinori Watanabe, Robert K. Brayton |
| 1993 | ICCD | Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | ICCD | Heuristic Minimization of Synchronous Relations. | Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton |
| 1993 | ICCD | Physically Realizable Gate Models. | Paul R. Stephan, Robert K. Brayton |
| 1993 | ICCD | Logic Optimization with Multi-Output Gates. | Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton |
| 1993 | VLSID | Minimization of Logic Functions Using Essential Signature Sets. | Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | CAV | Efficient | Ramin Hojati, Herv J. Touati, Robert P. Kurshan, Robert K. Brayton |
| 1992 | CAV | Automatic Reduction in CTL Compositional Model Checking. | Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton |
| 1992 | DAC | Solving the State Assignment Problem for Signal Transition Graphs. | Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | DAC | An Improved Synthesis Algorithm for Multiplexor-Based PGA's. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | DAC | Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. | Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | DAC | Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. | Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | DAC | On the Temporal Equivalence of Sequential Circuits. | Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | ICCAD | Automatic compositional minimization in CTL model checking. | Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton |
| 1992 | ICCAD | Valid clocking in wavepipelined circuits. | William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | ICCAD | Graph algorithms for clock schedule optimization. | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | ICCD | Delay Prediction for Technology-Independent Logic Equations. | Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton |
| 1992 | ICCD | On Relationship Between ITE and BDD. | William K. C. Lam, Robert K. Brayton |
| 1992 | ICCD | Sequential Circuit Design Using Synthesis and Optimization. | Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | DAC | A Framework for Satisfying Input and Output Encoding Constraints. | Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Performance Enhancement through the Generalized Bypass Transform. | Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni |
| 1991 | ICCAD | Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. | Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
| 1991 | ICCAD | On Clustering for Minimum Delay/Area. | Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Improved Logic Synthesis Algorithms for Table Look Up Architectures. | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCAD | Observability Relations and Observability Don't Cares. | Hamid Savoj, Robert K. Brayton |
| 1991 | ICCAD | Extracting Local Don't Cares for Network Optimization. | Hamid Savoj, Robert K. Brayton, Herv J. Touati |
| 1991 | ICCAD | Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. | Herv J. Touati, Hamid Savoj, Robert K. Brayton |
| 1991 | ICCAD | Heuristic Minimazation of Multiple-Valued Relations. | Yosinori Watanabe, Robert K. Brayton |
| 1991 | ICCD | Three-Level Decomposition with Application to PLDs. | Abdul A. Malik, David Harrison, Robert K. Brayton |
| 1991 | ICCD | Retiming of Circuits with Single Phase Transparent Latches. | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1991 | ICCD | Incremental Synthesis for Engineering Changes. | Yosinori Watanabe, Robert K. Brayton |
| 1990 | DAC | Reduced Offsets for Two-Level Multi-Valued Logic Minimization. | Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | DAC | Timing Analysis in Precharge/Unate Networks. | Patrick C. McGeer, Robert K. Brayton |
| 1990 | DAC | Logic Synthesis for Programmable Gate Arrays. | Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | DAC | The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. | Hamid Savoj, Robert K. Brayton |
| 1990 | ICCAD | MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. | Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | ICCAD | Performance Optimization of Pipelined Circuits. | Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | ICCAD | Timing Optimization with Testability Considerations. | Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng |
| 1990 | ICCAD | Algorithms for Discrete Function Manipulation. | Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton |
| 1990 | ICCAD | Implicit State Enumeration of Finite State Machines Using BDDs. | Herv J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | ICCD | The observability don't-care set and its approximations. | Patrick C. McGeer, Robert K. Brayton |
| 1989 | DAC | Efficient Prime Factorization of Logic Expressions. | Patrick C. McGeer, Robert K. Brayton |
| 1989 | DAC | Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. | Patrick C. McGeer, Robert K. Brayton |
| 1989 | DAC | Multi-level Logic Simplification Using Don't Cares and Filters. | Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1989 | ICCAD | SLIP: a software environment for system level interactive partitioning. | Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton |
| 1989 | ICCAD | An exact minimizer for Boolean relations. | Robert K. Brayton, Fabio Somenzi |
| 1989 | ICCAD | Consistency and observability invariance in multi-level logic synthesis. | Patrick C. McGeer, Robert K. Brayton |
| 1989 | ICCAD | Fast two-level logic minimizers for multi-level logic synthesis. | Hamid Savoj, Abdul A. Malik, Robert K. Brayton |
| 1989 | ICCD | Logic minimization for factored forms. | Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | ICCAD | XPSim: a MOS VLSI simulator. | Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton |
| 1988 | ICCAD | Don't cares and global flow analysis of Boolean networks. | Robert K. Brayton, Ellen M. Sentovich, Fabio Somenzi |
| 1988 | ICCAD | A modified approach to two-level logic minimization. | Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | ICCAD | Logic verification using binary decision diagrams in a logic synthesis environment. | Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | ICCAD | Timing optimization of combinational logic. | Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |