IEEE International Conference on Computer Design
ICCD
C
CORE rank
CORE rank (raw)
C
Fields of research
Computer Systems Engineering
Papers indexed
3,768
1988–2025
Papers per year
1988128 peak2025
Most published authors
ICCD papers
3,768 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2017 | Pulse Ring Oscillator Tuning via Pulse Dynamics. | Aditya Dalakoti, Merritt Miller, Forrest Brewer |
| 2017 | A Scale-Out Enterprise Storage Architecture. | Wonil Choi, Myoungsoo Jung, Mahmut T. Kandemir, Chita R. Das |
| 2017 | BioChipWork: Reverse Engineering of Microfluidic Biochips. | Huili Chen, Seetal Potluri, Farinaz Koushanfar |
| 2017 | A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function Evaluation. | Jing Chen, Xue Liu |
| 2017 | DLL-Assisted Clock Synchronization Method for Multi-Die ICs. | Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou |
| 2017 | Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. | Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra |
| 2017 | Low Latency Approximate Adder for Highly Correlated Input Streams. | Xiaoliang Chen, Ahmed M. Eltawil, Fadi J. Kurdahi |
| 2017 | ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning. | Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng |
| 2017 | Template Attack Based Deobfuscation of Integrated Circuits. | Abhishek Chakraborty, Yang Xie, Ankur Srivastava |
| 2017 | A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. | Yuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang |
| 2017 | Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators. | Ruizhe Cai, Ao Ren, Luhao Wang, Massoud Pedram, Yanzhi Wang |
| 2017 | Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. | Michaela Blott, Thomas B. Preuer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser |
| 2017 | Very Low Voltage (VLV) Design. | Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler |
| 2017 | NUPLet: A Photonic Based Multi-Chip NUCA Architecture. | Janibul Bashir, Smruti R. Sarangi |
| 2017 | Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs. | Qutaiba Alasad, Jiann-Shiun Yuan |
| 2017 | QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models. | Alif Ahmed, Prabhat Mishra |
| 2017 | RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance. | Armin Haj Aboutalebi, Lide Duan |
| 2016 | DOART: A low-power and low-latency Network-on-Chip. | Wen Zong, Qiang Xu |
| 2016 | ONAC: Optimal number of active cores detector for energy efficient GPU computing. | Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno |
| 2016 | Synthesis design strategies for energy-efficient microprocessors. | Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang |
| 2016 | A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs. | Xia Zhao, Sheng Ma, Chen Li, Lieven Eeckhout, Zhiying Wang |
| 2016 | Process variations-aware resistive associative processor design. | Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi |
| 2016 | A fast, fully verifiable, and hardware predictable ASIC design methodology. | Ping-Lin Yang, Malgorzata Marek-Sadowska |
| 2016 | HS-BAS: A hybrid storage system based on band awareness of Shingled Write Disk. | Wenjian Xiao, Huanqing Dong, Liuying Ma, Zhenjun Liu, Qiang Zhang |
| 2016 | A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance. | Xi-Yue Xiang, Saugata Ghose, Onur Mutlu, Nian-Feng Tzeng |
876–900 of 3,768← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design