| 2005 | Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. | Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li |
| 2005 | Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths. | Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu |
| 2005 | Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. | Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman |
| 2005 | Power-Efficient Wakeup Tag Broadcast. | Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin |
| 2005 | A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. | Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty |
| 2005 | Exact lower bound for the number of switches in series to implement a combinational logic cell. | Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, Andr Incio Reis |
| 2005 | Algorithmic and Architectural Design Methodology for Particle Filters in Hardware. | Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava |
| 2005 | Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. | Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini |
| 2005 | Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. | Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski |
| 2005 | A Feasibility Study of Subthreshold SRAM Across Technology Generations. | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy |
| 2005 | Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
| 2005 | A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. | Marco Antonio Ramrez, Adrin Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa |
| 2005 | Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
| 2005 | Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. | Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham |
| 2005 | Implementing Caches in a 3D Technology for High Performance Processors. | Kiran Puttaswamy, Gabriel H. Loh |
| 2005 | Restrictive Compression Techniques to Increase Level 1 Cache Capacity. | Prateek Pujara, Aneesh Aggarwal |
| 2005 | Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. | Luis A. Plana, Sam Taylor, Doug A. Edwards |
| 2005 | File System Interfaces for Embedded Software Development. | Bhanu Pisupati, Geoffrey Brown |
| 2005 | Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. | Song Peng, Rajit Manohar |
| 2005 | Latency Lags Bandwidth. | David A. Patterson |
| 2005 | Frame Buffer Energy Optimization by Pixel Prediction. | Kimish Patel, Enrico Macii, Massimo Poncino |
| 2005 | RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". | Won-Ho Park, Andreas Moshovos, Babak Falsafi |
| 2005 | Statistical Analysis Driven Synthesis of Asynchronous Systems. | Koji Ohashi, Mineo Kaneko |
| 2005 | Energy-Efficient Color Approximation for Digital LCD Interfaces. | Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino |
| 2005 | A Soft Error Monitor Using Switching Current Detection. | Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy |