| 2004 | Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs. | Kelvin Ng, Alan J. Hu, Jin Yang |
| 2004 | Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. | Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz |
| 2004 | An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems. | Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad |
| 2004 | IPC Driven Dynamic Associative Cache Architecture for Low Energy. | Sriram Nadathur, Akhilesh Tyagi |
| 2004 | Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. | Madhubanti Mukherjee, Ranga Vemuri |
| 2004 | Fetch Halting on Critical Load Misses. | Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss |
| 2004 | Network-on-Chip: The Intelligence is in The Wire. | Grard Mas, Philippe Martin |
| 2004 | Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. | Radu Marculescu, Diana Marculescu, Larry T. Pileggi |
| 2004 | A New Statistical Optimization Algorithm for Gate Sizing. | Murari Mani, Michael Orshansky |
| 2004 | Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. | Grigorios Magklis, Jos Gonzlez, Antonio Gonzlez |
| 2004 | Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. | Mirko Loghi, Luca Benini, Massimo Poncino |
| 2004 | Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. | Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra |
| 2004 | An Efficient Algorithm for Reconfiguring Shared Spare RRAM. | Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo |
| 2004 | XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. | Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma |
| 2004 | Low Power Test Data Compression Based on LFSR Reseeding. | Jinkyu Lee, Nur A. Touba |
| 2004 | A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs. | John C. Lach, Jason Brandon, Kevin Skadron |
| 2004 | A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. | Srivathsan Krishnamohan, Nihar R. Mahapatra |
| 2004 | Functional Illinois Scan Design at RTL. | Ho Fai Ko, Nicola Nicolici |
| 2004 | Adaptive Selection of an Index in a Texture Cache. | Chun-Ho Kim, Lee-Sup Kim |
| 2004 | Formal Hardware Verification based on Signal Correlation Properties. | Nikhil Kikkeri, Peter-Michael Seidel |
| 2004 | Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. | Joshua L. Kihm, Daniel A. Connors |
| 2004 | FPGA Emulation of Quantum Circuits. | Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka |
| 2004 | A High-Frequency Decimal Multiplier. | Robert D. Kenney, Michael J. Schulte, Mark A. Erle |
| 2004 | Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. | Dongku Kang, Hunsoo Choo, Kaushik Roy |
| 2004 | Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. | Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin |