| 2002 | Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. | Sanjukta Bhanja, N. Ranganathan |
| 2002 | Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. | Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino |
| 2002 | A Low Power Pseudo-Random BIST Technique. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
| 2002 | SIMD Extension to VLIW Multicluster Processors for Embedded Applications. | Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau |
| 2002 | Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. | Amirali Baniasadi, Andreas Moshovos |
| 2002 | Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction. | Stephanie Augsburger, Borivoje Nikolic |
| 2002 | Fault Dictionary Size Reduction through Test Response Superposition. | Baris Arslan, Alex Orailoglu |
| 2002 | Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. | Murali Annavaram, Trung A. Diep, John Paul Shen |
| 2002 | Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah |
| 2002 | Speculative Trace Scheduling in VLIW Processors. | Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan |
| 2002 | Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu |
| 2001 | Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. | Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan |
| 2001 | Compiler-Directed Classification of Value Locality Behavior. | Qing Zhao, David J. Lilja |
| 2001 | Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. | Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar |
| 2001 | Introduction to Generalized Symbolic Trajectory Evaluation. | Jin Yang, Carl-Johan H. Seger |
| 2001 | Gate Sizing to Eliminate Crosstalk Induced Timing Violation. | Tong Xiao, Malgorzata Marek-Sadowska |
| 2001 | Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. | Dong Xiang, Yi Xu |
| 2001 | Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. | Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang |
| 2001 | An Algorithm for Dynamically Reconfigurable FPGA Placement. | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang |
| 2001 | Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. | Kent E. Wires, Michael J. Schulte, James E. Stine |
| 2001 | Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem. | Jennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom |
| 2001 | High Performance Parallel Fault Simulation. | Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller |
| 2001 | Use of Local Memory for Efficient Java Execution. | Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
| 2001 | Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors. | Bhooshan S. Thakar, Gyungho Lee |
| 2001 | A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. | Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer |