| 2000 | A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages. | Yul Chu, Mabo Robert Ito |
| 2000 | Formal Verification of an Industrial System-on-a-Chip. | Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee |
| 2000 | Design of Instruction Stream Buffer with Trace Support for X86 Processors. | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
| 2000 | Static Timing Analysis with False Paths. | Haizhou Chen, Bing Lu, Ding-Zhu Du |
| 2000 | Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC | Yi-Kan Cheng, David Bearden, Kanti Suryadevara |
| 2000 | Architectural Support for Dynamic Memory Management. | J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan Lo |
| 2000 | Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. | Wander O. Cesrio, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa |
| 2000 | Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. | Qiang Cao, Josep Torrellas, H. V. Jagadish |
| 2000 | Efficient Place and Route for Pipeline Reconfigurable Architectures. | Srihari Cadambi, Seth Copen Goldstein |
| 2000 | Hybridizing and Coalescing Load Value Predictors. | Martin Burtscher, Benjamin G. Zorn |
| 2000 | Multilevel Reverse-Carry Adder. | Javier D. Bruguera, Toms Lang |
| 2000 | Current-Mode Threshold Logic Gates. | Sudhakar Bobba, Ibrahim N. Hajj |
| 2000 | An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. | Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani |
| 2000 | On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. | Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari |
| 2000 | Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications. | Wael M. Badawy, Magdy A. Bayoumi |
| 2000 | Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. | Tim Anderson, Sanjive Agarwala |
| 2000 | A Multi-Level Memory System Architecture for High-Performance DSP Applications. | Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley |
| 1999 | Compositional Software Synthesis of Communicating Processes. | Xiaohan Zhu, Bill Lin |
| 1999 | A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. | Kang Yi, Seong Yong Ohm |
| 1999 | BDD Decomposition for Efficient Logic Synthesis. | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
| 1999 | CAD Techniques for Embedded Systems-on-Silicon. | Wayne H. Wolf |
| 1999 | Benchmarking, Selection and Debugging of Microcontrollers. | Alan Weiss |
| 1999 | An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. | Qi Wang, Sarma B. K. Vrudhula |
| 1999 | Pursuing the Performance Potential of Dynamic Cache Line Sizes. | Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin |
| 1999 | On-Line BIST for Testing Analog Circuits. | Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis |