ACM International Symposium on Computer Architecture
ISCA
A*
CORE rank
CORE rank (raw)
A*
Acceptance rate
19.0% (2024)
Fields of research
Computer Systems Engineering · Distributed Computing and Systems Software · Software Engineering
Papers indexed
2,833
1973–2026
Papers per year
1973172 peak2026
Most published authors
ISCA papers
2,833 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2016 | All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory. | Jungrae Kim, Michael B. Sullivan, Sangkug Lym, Mattan Erez |
| 2016 | Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures. | Jungrae Kim, Michael B. Sullivan, Esha Choukse, Mattan Erez |
| 2016 | Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory. | Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay |
| 2016 | Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors. | Channoh Kim, Sungmin Kim, Hyeon-Gyu Cho, Doo-Young Kim, Jaehyeok Kim, Young H. Oh, Hakbeom Jang, Jae W. Lee |
| 2016 | Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL. | Donggyu Kim, Adam M. Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanovic |
| 2016 | RelaxFault Memory Repair. | Dong-Wan Kim, Mattan Erez |
| 2016 | Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement. | Akanksha Jain, Calvin Lin |
| 2016 | Decoupling Loads for Nano-Instruction Set Computers. | Ziqiang Huang, Andrew D. Hilton, Benjamin C. Lee |
| 2016 | Evaluation of an Analog Accelerator for Linear Algebra. | Yipeng Huang, Ning Guo, Mingoo Seok, Yannis P. Tsividis, Simha Sethumadhavan |
| 2016 | Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems. | Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler |
| 2016 | The SiLago Method: Next Generation VLSI Architectures and Design Methods. | Ahmed Hemani |
| 2016 | Accelerating Dependent Cache Misses with an Enhanced Memory Controller. | Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt |
| 2016 | EIE: Efficient Inference Engine on Compressed Deep Neural Network. | Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally |
| 2016 | Biscuit: A Framework for Near-Data Processing of Big Data Workloads. | Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang |
| 2016 | Base-Victim Compression: An Opportunistic Cache Compression Architecture. | Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney |
| 2016 | DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. | Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis |
| 2016 | Agile Paging: Exceeding the Best of Nested and Shadow Paging. | Jayneel Gandhi, Mark D. Hill, Michael M. Swift |
| 2016 | Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation. | Henry Duwe, Xun Jian, Daniel Petrisko, Rakesh Kumar |
| 2016 | ARM Virtualization: Performance and Architectural Implications. | Christoffer Dall, Shih-Wei Li, Jin Tack Lim, Jason Nieh, Georgios Koloventzos |
| 2016 | Vector Processors for Energy-Efficient Embedded Systems. | Daniel Palmer Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar, Krste Asanovic |
| 2016 | PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. | Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie |
| 2016 | Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems. | Hari Cherupalli, Rakesh Kumar, John Sartori |
| 2016 | Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks. | Eloi de Chrisey, Sylvain Guilley, Olivier Rioul, Darshana Jayasinghe |
| 2016 | LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. | Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie |
| 2016 | Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. | Yu-Hsin Chen, Joel S. Emer, Vivienne Sze |
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Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design
- AICSACM International Conference on Supercomputing