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ACM International Symposium on Computer Architecture

ISCA

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

19.0% (2024)

Fields of research

Computer Systems Engineering · Distributed Computing and Systems Software · Software Engineering

Papers indexed

2,833

1973–2026

Papers per year

1973172 peak2026

ISCA papers

2,833 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Internet-scale service infrastructure efficiency.James R. Hamilton
2009A memory system design framework: creating smart memories.Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz
2009The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization.Cagdas Dirik, Bruce L. Jacob
2009Stream chaining: exploiting multiple levels of correlation in data prefetching.Pedro Diaz, Marcelo Cintra
2009Phastlane: a rapid transit optical routing network.Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi
2009Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Hkan Zeffer, Marc Tremblay
2009End-to-end register data-flow continuous self-test.Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio Gonzlez
2009InvisiFence: performance-transparent memory ordering in conventional multiprocessors.Colin Blundell, Milo M. K. Martin, Thomas F. Wenisch
2009Multi-execution: multicore caching for data-similar executions.Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong
2009Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.Abhishek Bhattacharjee, Margaret Martonosi
2009Achieving predictable performance through better memory controller placement in many-core CMPs.Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti
2008Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2008Corona: System Implications of Emerging Nanophotonic Technology.Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2008Achieving Out-of-Order Performance with Almost In-Order Complexity.Francis Tseng, Yale N. Patt
2008A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi
2008Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors.Radu Teodorescu, Josep Torrellas
2008Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.Alex Shye, Berkin zisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary
2008Flexible Decoupled Transactional Memory Support.Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2008A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston
2008Intra-disk Parallelism: An Idea Whose Time Has Come.Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan
2008Counting Dependence Predictors.Franziska Roesner, Doug Burger, Stephen W. Keckler
2008A Two-Level Load/Store Queue Based on Execution Locality.Miquel Perics, Adrin Cristal, Francisco J. Cazorla, Rubn Gonzlez, Alexander V. Veidenbaum, Daniel A. Jimnez, Mateo Valero
2008MIRA: A Multi-layered On-Chip Interconnect Router Architecture.Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems.Onur Mutlu, Thomas Moscibroda
2008DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently.Pablo Montesinos, Luis Ceze, Josep Torrellas
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