| 1999 | The Program Decision Logic Approach to Predicated Execution. | David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu |
| 1998 | Performance Modeling and Code Partitioning for the DS Architecture. | Yinong Zhang, George B. Adams III |
| 1998 | Alternative Implementations of Two-Level Adaptive Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1998 | Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1998 | Threaded Multiple Path Execution. | Steven Wallace, Brad Calder, Dean M. Tullsen |
| 1998 | Retrospective: The Cedar System. | Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan |
| 1998 | Simultaneous Multithreading: Maximizing On-Chip Parallelism. | Dean M. Tullsen, Susan J. Eggers, Henry M. Levy |
| 1998 | Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism. | Dean M. Tullsen, Susan J. Eggers, Henry M. Levy |
| 1998 | Increasing TLB Reach Using Superpages Backed by Shadow Memory. | Mark R. Swanson, Leigh Stoller, John B. Carter |
| 1998 | Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors. | Vijayaraghavan Soundararajan, Mark A. Heinrich, Ben Verghese, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy |
| 1998 | Analytic Evaluation of Shared-memory Systems with ILP Processors. | Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood |
| 1998 | Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. | Gurindar S. Sohi, Sriram Vajapeyam |
| 1998 | Multiscalar Processors. | Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar |
| 1998 | Retrospective: Multiscalar Processors. | Gurindar S. Sohi |
| 1998 | Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. | Gurindar S. Sohi |
| 1998 | Implementation of Precise Interupts in Pipelined Processors. | James E. Smith, Andrew R. Pleszkun |
| 1998 | Decoupled Access/Execute Computer Architectures. | James E. Smith |
| 1998 | A Study of Branch Prediction Strategies. | James E. Smith |
| 1998 | Retrospective: Implementing Precise Interrupts in Pipelined Processors. | James E. Smith |
| 1998 | Retrospective: Decoupled Access/Execute Architectures. | James E. Smith |
| 1998 | Retrospective: A Study of Branch Prediction Strategies. | James E. Smith |
| 1998 | Retrospective: An Instruction Timing Model of CPU Performance. | Leonard J. Shustek, Bernard L. Peuto |
| 1998 | Modeling Program Predictability. | Yiannakis Sazeides, James E. Smith |
| 1998 | Tempest and Typhoon: User-Level Shared Memory. | Steven K. Reinhardt, James R. Larus, David A. Wood |
| 1998 | Retrospective: Tempest and Typhoon: User-Level Shared Memory. | Steven K. Reinhardt, James R. Larus, David A. Wood |