| 1995 | An investigation of the performance of various instruction-issue buffer topologies. | Stphan Jourdan, Pascal Sainrat, Daniel Litaize |
| 1995 | Partitioned register file for TTAs. | Johan Janssen, Henk Corporaal |
| 1995 | A limit study of local memory requirements using value reuse profiles. | Andrew S. Huang, John Paul Shen |
| 1995 | Region-based compilation: an introduction and motivation. | Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau |
| 1995 | Self-regulation of workload in the Manchester Data-Flow computer. | John R. Gurd, David F. Snelling |
| 1995 | Performance issues in correlated branch prediction schemes. | Nicholas C. Gloy, Michael D. Smith, Cliff Young |
| 1995 | The M-Machine multicomputer. | Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee |
| 1995 | Partial resolution in branch target buffers. | Barry S. Fagin, Kathryn Russell |
| 1995 | Stage scheduling: a technique to reduce the register requirements of a modulo schedule. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1995 | Register allocation for predicated code. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1995 | Control flow prediction with tree-like subgraphs for superscalar processors. | Simonjit Dutta, Manoj Franklin |
| 1995 | Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation. | Jack W. Davidson, Sanjay Jinturkar |
| 1995 | Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. | Thomas M. Conte, Sumedh W. Sathaye |
| 1995 | An effective programmable prefetch engine for on-chip caches. | Tien-Fu Chen |
| 1995 | Alternative implementations of hybrid branch predictors. | Po-Yung Chang, Eric Hao, Yale N. Patt |
| 1995 | The predictability of branches in libraries. | Brad Calder, Dirk Grunwald, Amitabh Srivastava |
| 1995 | A system level perspective on branch architecture performance. | Brad Calder, Dirk Grunwald, Joel S. Emer |
| 1995 | Efficient instruction scheduling using finite state automata. | Vasanth Bala, Norman Rubin |
| 1995 | Zero-cycle loads: microarchitecture support for reducing load latency. | Todd M. Austin, Gurindar S. Sohi |
| 1995 | Petri net versus modulo scheduling for software pipelining. | Vicki H. Allan, U. R. Shah, K. M. Reddy |
| 1995 | The performance impact of incomplete bypassing in processor pipelines. | Pritpal S. Ahuja, Douglas W. Clark, Anne Rogers |
| 1994 | Data relocation and prefetching for programs with large data sets. | Yoji Yamada, John C. Gyllenhaal, Grant E. Haab, Wen-mei W. Hwu |
| 1994 | Static branch frequency and program profile analysis. | Youfeng Wu, James R. Larus |
| 1994 | Software pipelining with register allocation and spilling. | Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis |
| 1994 | Analysis of the conditional skip instructions of the HP precision architecture. | Jonathan P. Vogel, Bruce K. Holmer |