| 1994 | The effects of predicated execution on branch prediction. | Gary S. Tyson |
| 1994 | A study of pointer aliasing for software pipelining using run-time disambiguation. | Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu |
| 1994 | Minimizing branch misprediction penalties for superpipelined processors. | Ching-Long Su, Alvin M. Despain |
| 1994 | Facilitating superscalar processing via a combined static/dynamic register renaming scheme. | Eric Sprangle, Yale N. Patt |
| 1994 | Height reduction of control recurrences for ILP processors. | Michael S. Schlansker, Vinod Kathail, Sadun Anik |
| 1994 | A high-performance microarchitecture with hardware-programmable functional units. | Rahul Razdan, Michael D. Smith |
| 1994 | Iterative modulo scheduling: an algorithm for software pipelining loops. | B. Ramakrishna Rau |
| 1994 | Techniques for compressing program address traces. | Andrew R. Pleszkun |
| 1994 | Theoretical modeling of superscalar processor performance. | Derek B. Noonburg, John Paul Shen |
| 1994 | Characterizing the impact of predicated execution on branch prediction. | Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu |
| 1994 | Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution. | Raymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu |
| 1994 | Cache designs with partial address matching. | Lishing Liu |
| 1994 | Register file port requirements of transport triggered architectures. | Jan Hoogerbrugge, Henk Corporaal |
| 1994 | The effect of speculatively updating branch history on branch prediction accuracy, revisited. | Eric Hao, Po-Yung Chang, Yale N. Patt |
| 1994 | Minimizing register requirements under resource-constrained rate-optimal software pipelining. | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
| 1994 | A comparison of two pipeline organizations. | Michael Golden, Trevor N. Mudge |
| 1994 | A fill-unit approach to multiple instruction issue. | Manoj Franklin, Mark Smotherman |
| 1994 | Minimum register requirements for a modulo schedule. | Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham |
| 1994 | Reducing memory traffic with CRegs. | Peter Dahl, Matthew T. O'Keefe |
| 1994 | Using branch handling hardware to support profile-driven optimization. | Thomas M. Conte, Burzin A. Patel, J. Stan Cox |
| 1994 | Branch classification: a new mechanism for improving branch predictor performance. | Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt |
| 1994 | The anatomy of the register file in a multiscalar processor. | Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi |
| 1994 | Dynamic memory disambiguation for array references. | David Bernstein, Doron Cohen, Dror E. Maydan |
| 1993 | Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. | Tse-Yu Yeh, Yale N. Patt |
| 1993 | Two-ported cache alternatives for superscalar processors. | Andrew Wolfe, Rodney Boleyn |