| 1991 | A Quantitative Analysis of Locality in Dataflow Programs. | William Marcus Miller, Walid A. Najjar, A. P. Wim Bhm |
| 1991 | Register/File/Cache Microarchitecture Study Using VHDL. | Samarina Makhdoom, Daniel Tabak, Richard Auletta |
| 1991 | Executing Loops on a Fine-Grained MIMD Architecture. | Sunah Lee, Rajiv Gupta |
| 1991 | ALPS: An Algorithm for Pipeline Data Path Synthesis. | Ramesh Karri, Alex Orailoglu |
| 1991 | Software Pipelining: An Evaluation of Enhanced Pipelining. | Reese B. Jones, Vicki H. Allan |
| 1991 | Software Pipelining for Transport-Triggered Architectures. | Jan Hoogerbrugge, Henk Corporaal, Hans M. Mulder |
| 1991 | Viewing Instruction Set Design as an Optimization Problem. | Bruce K. Holmer, Alvin M. Despain |
| 1991 | Workload and Implementation Considerations for Dynamic Base Register Caching. | Matthew K. Farrens, Arvin Park |
| 1991 | Architecture and Programming of a VLIW Style Programmable Video Signal Processor. | Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers |
| 1991 | On Reconfigurable On-Chip Data Caches. | Fredrik Dahlgren, Per Stenstrm |
| 1991 | Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. | William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu |
| 1991 | Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. | Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu |
| 1991 | The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. | Michael Butler, Yale N. Patt |
| 1991 | Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. | Maurcio Breternitz Jr., John Paul Shen |
| 1991 | Strategies for Branch Target Buffers. | Brian K. Bray, Michael J. Flynn |
| 1991 | Code Duplication: An Assist for Global Instruction Scheduling. | David Bernstein, Doron Cohen, Hugo Krawczyk |
| 1991 | An Analysis of the Information Content of Address Reference Streams. | Jeffrey C. Becker, Arvin Park, Matthew K. Farrens |
| 1991 | Genetic Algorithms and Instruction Scheduling. | Steven J. Beaty |
| 1990 | Ideograph/Ideogram: framework/hardware for eager evaluation. | S. ShouHan Wang, Augustus K. Uht |
| 1990 | Post-compaction register assignment in a retargetable compiler. | Philip H. Sweany, Steven J. Beaty |
| 1990 | A software pipelining based VLIW architecture and optimizing compiler. | Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu |
| 1990 | SMDSS - a structured microcode development and simulation system. | Djahida Smati, Jerry P.-C. Hwang, Christos A. Papachristou |
| 1990 | Microprogramming heritage of RISC design. | Liwen Shih |
| 1990 | An instruction reoderer for pipelined computers. | Jong-Jiann Shieh, Christos A. Papachristou |
| 1990 | The selection of optimal cache lines for microprocessor-based controllers. | Tsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin |