| 2024 | Design and Analysis of an Area and Power Efficient Programmable Delay Cell. | Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal |
| 2024 | Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel. | Minal Bisen, Kapil Jainwal, Nitin Khanna |
| 2024 | Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA. | Nidhee Bhuwal, Kamal Solanki, Manoj Kumar Majumder, Deepika Gupta |
| 2024 | Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA. | Tamonash Bhattacharyya, Prasun Ghosal, Sonam, Sujay Deb |
| 2024 | Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. | Pritam Bhattacharjee, Alak Majumder |
| 2024 | Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement. | Pooja Beniwal, Sneh Saurabh |
| 2024 | Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. | Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana |
| 2024 | Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application. | Shriharsh Prasad Behera, Mahesh Vaidya, Alok Naugarhiya |
| 2024 | Reconfigurable Processing-in-Memory Architecture for Data Intensive Applications. | Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao |
| 2024 | On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules. | Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya |
| 2024 | Analysis of the Effects of Crosstalk Errors on Various Quantum Circuits. | Soumen Bajpayee, Imon Mukherjee |
| 2024 | FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing. | Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, Joycee Mekie |
| 2024 | Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. | Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor |
| 2024 | Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. | Noa Aflalo, Eilam Yalon, Shahar Kvatinsky |
| 2024 | Broadband spectrum generation in Silicon nanocrystal-based dual-slot waveguide. | Somen Adhikary, Ritesh Das, Mousumi Basu |
| 2023 | Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. | Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta |
| 2023 | Machine Learning-based model for Single Event Upset Current Prediction in 14nm FinFETs. | Vibhu, Sparsh Mittal, Vivek Kumar |
| 2023 | Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. | Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri |
| 2023 | Efficient 3D Modeling Methodology for High-Speed Channels. | Sivalingam Thirubalan, Suresh Kumar Kopparti, Desmond Tan Hai Peng |
| 2023 | Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes. | Krishnan Sukumar, Santosh Vodnala, Ravindra Ayyagari, Animesh Jain, Thanapandi Ganesan, Rajesh R |
| 2023 | Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. | Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma |
| 2023 | A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR. | Sowmyashree S, Hitesh Shrimali |
| 2023 | An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. | Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal |
| 2023 | Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. | Suriya Srinivasan, Ranga Vemuri |
| 2023 | Enhanced Performance Parameters of Magnetic Tunnel Junction with Composite Dielectric Barrier. | Reshma Sinha, Jasdeep Kaur |