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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
19923-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set.Irith Pomeranz, Sudhakar M. Reddy
1992Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines.Marek A. Perkowski, William Zhao, Douglas V. Hall
1992An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing.Rajat Kumar Pal, Ajit Pal
1992Data Path Synthesis With Global Time Constraint.Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar
1992N2S: An Automatic Netlist to Schematic generator.B. Naveen, A. Savargaonkar, K. S. Raghunathan
1992System Level Specification and Synthesis.Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
1992WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits.S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand
1992OPSYN - OASYS Based Pseudosynthesis Tool.N. S. Nagaraj
1992Benchmarking Array Comparators.Samiha Mourad
1992A New algorithm for combined PLA folding.Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose
1992Estimating the Complexity of Synthesized Designs from FSM Specifications.Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
1992An Efficient State Assignment Technique using Least Commitment and Constraint Propagation Techniques.Biswadip Mitra, Parimal Pal Chaudhuri
1992Combined Synthesis of Easily Testable Datapath and Control Designs.Biswadip Mitra, Parimal Pal Chaudhuri
1992Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata.Susanta Misra, Biswadip Mitra, S. Sengupta, Parimal Pal Chaudhuri
1992On Bridging Faults in ECL Circuits.Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya
1992Design and Implementation of High Speed RNS Input-Output Converters.Kalpesh D. Mehta, V. R. Sudershan
1992A System for Behavior Extraction from FPGA Implementations of Synchronous Designs.Mahesh Mehendale
1992Interconnect Optimization Techniques in Data Path Synthesis.Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose
1992A Force Directed Hill-Climbing Placement Algorithm.Rajib Mall, Lalit M. Patnaik
1992Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low Temperature.Chinmay K. Maiti
1992Quad Asynchronous Communication Element (ACE) with FIFO.S. Uma Mahesh, Marty Long, Laura Simmons
1992Optimization Techniques for Pipelined Scheduling.Donald A. Lobo, Barry M. Pangrle
1992A New Accurate and Efficient Timing Simulator.Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1992A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas.Manu Lauria, Shashi Kumar, Anshul Kumar
1992Logic Design and Synthesis with IEEE Logic Symbols in the DEMET System.Jukka Lahti, Jorma Kivel
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