| 2021 | An Automated Tool for Implementing Deep Neural Networks on FPGA. | Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia |
| 2021 | A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. | Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta |
| 2021 | A 3.55 dB NF Ultra-Compact Noise-Optimized LNA for 5G mm-Wave Bands in 65nm CMOS. | Noble Sebastian, Chavva Subbareddy, Immanuel Raja |
| 2021 | Hardware Accelerator for Dual Standard Deblocking Filter. | P. Saravanan, B. Syndia Priyadarshini, P. Vignesh Kanna, P. Vaishnavi |
| 2021 | Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. | Prasenjit Saha, Hema Sai Kalluru, Zia Abbas |
| 2021 | Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
| 2021 | Novel Census Transform Hardware IP. | Anish Reghunath, Mihir Mody, Hetul Sanghvi, Ankur |
| 2021 | A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology. | Nisarga Ramesh, Syed Javed Gaggatur |
| 2021 | Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients. | Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen |
| 2021 | Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. | Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna |
| 2021 | Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. | Arnab Raha, Sang Kyun Kim, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Raymond Sung, Cormac Brick, Gautham N. Chinya |
| 2021 | Instruction Controlled In-memory Sorting on Memristor Crossbars. | Sumanta Pyne |
| 2021 | High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. | Dharmaray Nedalgi, Saroja V. Siddamal |
| 2021 | A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. | Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini |
| 2021 | Game Theory-Based Parameter-Tuning for Path Planning of UAVs. | Diksha Moolchandani, Geesara Prathap, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti R. Sarangi |
| 2021 | A Low Latency Stochastic Square Root Circuit. | Shyamali Mitra, Debojyoti Banerjee, Mrinal K. Naskar |
| 2021 | Creating Fastest Self timing Reference Path for High Speed Memory Designs. | Krashna Nand Mishra, Yogeshbhai Vallabhbhai Patel |
| 2021 | ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. | Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers |
| 2021 | An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors. | Sudipa Mandal, Krushna Gaurkar, Pallab Dasgupta, Aritra Hazra |
| 2021 | Prospects of Two-dimensional Material-based Field-Effect Transistors for Analog/RF Applications. | Arjun Kumar, Akhilesh Rawat, Brajesh Rawat |
| 2021 | PositGen-A Verification Suite for Posit Arithmetic. | Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine |
| 2021 | Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock Logic. | Prasad Kulkarni, Sahil Garg, Shubhi Agrawal, Maryam Shojaei Baghini |
| 2021 | Efficient Hierarchical Post-Silicon Validation and Debug. | Pandy Kalimuthu, Kanad Basu, Benjamin Carrin Schfer |
| 2021 | P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. | Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine |
| 2021 | A Multiply Accumulator for Stochastic Numbers Without Scaling Errors. | Katsuhiro Ichikawa, Shigeru Yamashita |