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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2016Emulation - Smart Way of Power Estimation and Power Aware Verfication.Gaurav Saharawat, Praveen Shukla, Saurabh Jain, Subash Nayak
2016A Modified Hill Climbing Based Watershed Algorithm and Its Real Time FPGA Implementation.Pradipta Roy, Prabir K. Biswas, Binoy Kumar Das
2016A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Receiver Frond End with Split TCAs in 180nm CMOS.Sesha Sairam Regulagadda, Purushothama Chary, Rizwan Shaik Peerla, Mohd Abdul Naseeb, Amit Acharyya, Pachamuthu Rajalakshmi, Ashudeb Dutta
2016Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage.Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri
2016A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS Technology.R. G. Raghavendra, Balbeer Singh Rathor
2016Test Generation for Hybrid Systems Using Clustering and Learning Techniques.Sudhi Proch, Prabhat Mishra
2016Al/HfO2/Si Gate Stack with Improved Physical and Electrical Parameters.Rakesh Prasher, Devi Dass, Rakesh Vaid
2016A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta Modulator.Jos A. V. Prakash, Babita R. Jose, Jimson Mathew
2016A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier.M. V. Prajwal, B. S. Srinivas, S. Shodhan, M. K. Jayaram Reddy, Tonse Laxminidhi
2016An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication.Ashish Kumar Pradhan, Soumitra Kumar Nandy
2016Demystifying Time Varying Circuits and Systems.Shanthi Pavan, Nagendra Krishnapura
2016Using Tweaks to Design Fault Resistant Ciphers.Sikhar Patranabis, Debapriya Basu Roy, Debdeep Mukhopadhyay
2016A Modified SRAM Based Low Power Memory Design.Apoorva Pathak, Divyesh Sachan, Harish Peta, Manish Goswami
2016Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.Harsh N. Patel, Farah B. Yahya, Benton H. Calhoun
2016Security Metrics for Power Based SCA Resistant Hardware Implementation.Jungmin Park, Akhilesh Tyagi
2016FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay.Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
2016The Future of NoCs: New Technologies and Architectures.Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani
2016Symptomatic Bug Localization for Functional Debug of Hardware Designs.Debjit Pal, Shobha Vasudevan
2016A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop.Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta
2016Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.Ayan Palchaudhuri, Anindya Sundar Dhar
2016Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors.Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra
2016Digital Testing of ICs for Automotive Applications.Nilanjan Mukherjee, Janusz Rajski
2016Stochastic Number Generation with Few Inputs.Ritsuko Muguruma, Shigeru Yamashita
2016Power Optimization of LNA for LTE Receiver.Vinaya M. M., Roy Paily, Anil Mahanta
2016An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems.Saroj Mondal, Roy P. Paily
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