| 2025 | AFT | Modeling Loss-Versus-Rebalancing in Automated Market Makers via Continuous-Installment Options. | Srisht Fateh Singh, Reina Ke Xin Li, Samuel Gaskin, Yuntao Wu, Jeffrey Klinck, Panagiotis Michalopoulos, Zissis Poulos, Andreas G. Veneris |
| 2024 | ICSE | Safeguarding DeFi Smart Contracts against Oracle Deviations. | Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long |
| 2019 | ASPDAC | Suspect2vec: a suspect prediction model for directed RTL debugging. | Neil Veira, Zissis Poulos, Andreas G. Veneris |
| 2019 | FMCAD | Chasing Minimal Inductive Validity Cores in Hardware Model Checking. | Ryan Berryhill, Andreas G. Veneris |
| 2019 | IJCAI | Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. | Neil Veira, Brian Keng, Kanchana Padmanabhan, Andreas G. Veneris |
| 2018 | DATE | Suspect set prediction in RTL bug hunting. | Neil Veira, Zissis Poulos, Andreas G. Veneris |
| 2018 | SAT | Finding All Minimal Safe Inductive Sets. | Ryan Berryhill, Alexander Ivrii, Andreas G. Veneris |
| 2017 | ASPDAC | An extensible perceptron framework for revision RTL debug automation. | John Adler, Ryan Berryhill, Andreas G. Veneris |
| 2017 | FMCAD | Learning support sets in IC3 and Quip: The good, the bad, and the ugly. | Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris |
| 2016 | ASPDAC | A complete approach to unreachable state diagnosability via property directed reachability. | Ryan Berryhill, Andreas G. Veneris |
| 2016 | DATE | Root-cause analysis for memory-locked errors. | John Adler, Djordje Maksimovic, Andreas G. Veneris |
| 2016 | ISAIM | Efficient Selection of Suspect Sets in Unreachable State Diagnosis. | Ryan Berryhill, Andreas G. Veneris |
| 2015 | DATE | Automated rectification methodologies to functional state-space unreachability. | Ryan Berryhill, Andreas G. Veneris |
| 2015 | ICCD | Clustering-based revision debug in regression verification. | Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos |
| 2015 | IOLTS | Mining simulation metrics for failure triage in regression testing. | Zissis Poulos, Andreas G. Veneris |
| 2014 | ASPDAC | Automated debugging of missing assumptions. | Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le |
| 2014 | ICCAD | Multiple clock domain synchronization in a QBF-based verification environment. | Djordje Maksimovic, Bao Le, Andreas G. Veneris |
| 2014 | ITC | Clustering-based failure triage for RTL regression debugging. | Zissis Poulos, Andreas G. Veneris |
| 2013 | ASPDAC | Reviving erroneous stability-based clock-gating using partial Max-SAT. | Bao Le, Dipanjan Sengupta, Andreas G. Veneris |
| 2013 | IOLTS | Accelerating post silicon debug of deep electrical faults. | Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos |
| 2013 | IOLTS | A failure triage engine based on error trace signature extraction. | Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris |
| 2013 | ISLPED | Early detection of current hot spots in power gated designs. | Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris |
| 2012 | ASPDAC | On error tolerance and Engineering Change with Partially Programmable Circuits. | Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita |
| 2012 | ASPDAC | Automated data analysis techniques for a modern silicon debug environment. | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita |
| 2012 | DAC | Path directed abstraction and refinement in SAT-based design debugging. | Brian Keng, Andreas G. Veneris |
| 2012 | DATE | Non-solution implications using reverse domination in a modern SAT-based debugging environment. | Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris |
| 2012 | DATE | Leveraging reconfigurability to raise productivity in FPGA functional debug. | Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le |
| 2012 | FMCAD | Automated debugging of missing input constraints in a formal verification environment. | Brian Keng, Andreas G. Veneris |
| 2011 | ASPDAC | Managing complexity in design debugging with sequential abstraction and refinement. | Brian Keng, Andreas G. Veneris |
| 2011 | ASPDAC | From RTL to silicon: The case for automated debug. | Andreas G. Veneris, Brian Keng, Sean Safarpour |
| 2011 | DATE | Automated debugging of SystemVerilog assertions. | Brian Keng, Sean Safarpour, Andreas G. Veneris |
| 2011 | ICCAD | Debugging with dominance: On-the-fly RTL debug solution implications. | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour |
| 2010 | ASPDAC | Managing verification error traces with bounded model debugging. | Sean Safarpour, Andreas G. Veneris, Farid N. Najm |
| 2010 | DATE | Leveraging dominators for preprocessing QBF. | Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus |
| 2009 | DAC | The day Sherlock Holmes decided to do EDA. | Andreas G. Veneris, Sean Safarpour |
| 2009 | DATE | Automated data analysis solutions to silicon debug. | Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris |
| 2009 | DATE | Sequential logic rectifications with approximate SPFDs. | Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith |
| 2009 | FMCAD | Scaling VLSI design debugging with interpolation. | Brian Keng, Andreas G. Veneris |
| 2008 | ICCAD | A succinct memory model for automated design debugging. | Brian Keng, Hratch Mangassarian, Andreas G. Veneris |
| 2008 | IOLTS | On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
| 2008 | ISLPED | A physical level study and optimization of CAM-based checkpointed register alias table. | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
| 2007 | ASPDAC | Trace Compaction using SAT-based Reachability Analysis. | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian |
| 2007 | ASPDAC | Automating Logic Rectification by Approximate SPFDs. | Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton |
| 2007 | DATE | Maximum circuit activity estimation using pseudo-boolean satisfiability. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir |
| 2007 | DATE | Abstraction and refinement techniques in automated design debugging. | Sean Safarpour, Andreas G. Veneris |
| 2007 | FMCAD | Improved Design Debugging Using Maximum Satisfiability. | Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah |
| 2007 | ICCAD | A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith |
| 2007 | ISLPED | On the latency, energy and area of checkpointed, superscalar register alias tables. | Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni |
| 2006 | DAC | Efficient SAT-based Boolean matching for FPGA technology mapping. | Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan |
| 2006 | DATE | On the relation between simulation-based and SAT-based diagnosis. | Grschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2006 | ISCAS | Integrating observability don't cares in all-solution SAT solvers. | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2006 | ISLPED | L-CBF: a low-power, fast counting bloom filter architecture. | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
| 2006 | ITC | Seamless Integration of SER in Rewiring-Based Design Space Exploration. | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
| 2006 | VTS | Session Abstract. | Andreas G. Veneris, Yiorgos Makris |
| 2005 | DATE | Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
| 2005 | ICCAD | Post-verification debugging of hierarchical designs. | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
| 2004 | ASPDAC | Design diagnosis using Boolean satisfiability. | Alexander Smith, Andreas G. Veneris, Anastasios Viglas |
| 2004 | DATE | Managing Don't Cares in Boolean Satisfiability. | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee |
| 2004 | ICCAD | Debugging sequential circuits using Boolean satisfiability. | Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir |
| 2004 | ISCAS | Fault equivalence and diagnostic test generation using ATPG. | Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri |
| 2003 | ASPDAC | Logic verification based on diagnosis techniques. | Andreas G. Veneris, Alexander Smith, Magdy S. Abadir |
| 2003 | ITC | Extraction Error Diagnosis and Correction in High-Performance Designs. | Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris |
| 2002 | DATE | Incremental Diagnosis and Correction of Multiple Faults and Errors. | Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir |
| 2002 | ISCAS | Design rewiring for power minimization [logic design]. | Mandana Amiri, Andreas G. Veneris, Ivor Ting |
| 2002 | ITC | Incremental Diagnosis of Multiple Open-Interconnects. | Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi |
| 2002 | ITC | Design Rewiring Using ATPG. | Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri |
| 2001 | ASPDAC | Design rewiring based on diagnosis techniques. | Andreas G. Veneris, Magdy S. Abadir, Ivor Ting |
| 1999 | ISCAS | Correcting multiple design errors in digital VLSI circuits. | Andreas G. Veneris, Ibrahim N. Hajj |
| 1999 | VTS | Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. | Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs |