Boyang Du
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
5
Active years
2013–2018
Best venue rank
C
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ETS | On the mitigation of single event transients on flash-based FPGAs. | Sarah Azimi, Boyang Du, Luca Sterpone |
| 2018 | IOLTS | About the functional test of the GPGPU scheduler. | Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone |
| 2017 | ITC | Fault tolerant electronic system design. | Boyang Du, Luca Sterpone |
| 2016 | DDECS | FPGA-controlled PCBA power-on self-test using processor's debug features. | Boyang Du, Ernesto Snchez, Matteo Sonza Reorda, Julio Prez Acle, Anton Tsertov |
| 2016 | ETS | A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs. | Boyang Du, Luca Sterpone, David Merodio Codinachs |
| 2016 | IAS | Consensus of Discrete-Time Linear Networked Multi-agent Systems Subject to Actuator Saturation. | Boyang Du, Guoliang Zhang, Jun Xu, Jing Zeng, Yong Zhang |
| 2016 | IOLTS | Scalable FPGA graph model to detect routing faults. | Luca Sterpone, Gianpiero Cabodi, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Boyang Du |
| 2014 | ETS | Analysis and mitigation of single event effects on flash-based FPGAS. | Luca Sterpone, Boyang Du |
| 2014 | IOLTS | A new solution to on-line detection of Control Flow Errors. | Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-Garca, Almudena Lindoso, Luis Entrena |
| 2013 | IOLTS | Exploiting the debug interface to support on-line test of control flow errors. | Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-Garca, Almudena Lindoso, Luis Entrena |