| 2025 | ITC | An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists. | Aric Fowler, Carl Sechen, Yiorgos Makris |
| 2024 | VTS | Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. | Apurva Jain, Thomas Broadfoot, Carl Sechen, Yiorgos Makris |
| 2023 | DATE | Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. | Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen |
| 2020 | DATE | An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. | Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrin Schfer, Carl Sechen |
| 2020 | ISCAS | Optimal Standard Cell Library Composition for 7nm. | Vibhav Kumarswami Salimath, Carl Sechen |
| 2020 | ISCAS | CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. | Mustafa M. Shihab, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Jingxiang Tian, William Swartz, Carl Sechen, Yiorgos Makris |
| 2020 | VTS | ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. | Mustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris |
| 2019 | DAC | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. | Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaa, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu |
| 2019 | DATE | Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. | Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrin Schfer, Carl Sechen, Yiorgos Makris |
| 2017 | DATE | A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. | Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen |
| 2013 | ISLPED | Low-voltage low-overhead asynchronous logic. | Akshay Sridharan, Carl Sechen, Roozbeh Jafari |
| 2012 | DATE | Post-synthesis leakage power minimization. | Mohammad Rahman, Carl Sechen |
| 2011 | DAC | Power reduction via separate synthesis and physical libraries. | Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen |
| 2011 | DATE | Power reduction via near-optimal library-based cell-size selection. | Mohammad Rahman, Hiran Tennakoon, Carl Sechen |
| 2007 | ICCD | Post-layout comparison of high performance 64b static adders in energy-delay space. | Sheng Sun, Carl Sechen |
| 2006 | ISCAS | Post-layout energy-delay analysis of parallel multipliers. | Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen |
| 2005 | DAC | Efficient and accurate gate sizing with piecewise convex delay models. | Hiran Tennakoon, Carl Sechen |
| 2004 | DAC | Efficient timing closure without timing driven placement and routing. | Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen |
| 2003 | DAC | Libraries: lifejacket or straitjacket. | Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar |
| 2003 | ISCAS | A low power delayed-clocks generation and distribution system. | Su Kio, Kian Haur Chong, Carl Sechen |
| 2002 | ICCAD | WTA: waveform-based timing analysis for deep submicron circuits. | Larry McMurchie, Carl Sechen |
| 2002 | ICCAD | Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. | Hiran Tennakoon, Carl Sechen |
| 2002 | ICCAD | Optimized power-delay curve generation for standard cell ICs. | Miodrag Vujkovic, Carl Sechen |
| 2001 | DAC | Panel: (When) Will FPGAs Kill ASICs? | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen |
| 2001 | DATE | Automatic datapath tile placement and routing. | Tatjana Serdar, Carl Sechen |
| 2001 | ICCAD | Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. | Jovanka Ciric, Carl Sechen |
| 2000 | DATE | Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. | Jovanka Ciric, Gin Yee, Carl Sechen |
| 2000 | ICCD | Output Prediction Logic: A High-Performance CMOS Design Technique. | Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen |
| 1999 | ICCAD | AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. | Tatjana Serdar, Carl Sechen |
| 1999 | ICCD | Design and Synthesis of Monotonic Circuits. | Tyler Thorp, Gin Yee, Carl Sechen |
| 1998 | DAC | Timing and Crosstalk Driven Area Routing. | Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen |
| 1998 | ICCAD | Domino logic synthesis using complex static gates. | Tyler Thorp, Gin Yee, Carl Sechen |
| 1997 | DAC | The Future of Custom Cell Generation in Physical Synthesis. | Martin Lefebvre, David Marple, Carl Sechen |
| 1997 | DATE | Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. | Le-Chin Eugene Liu, Carl Sechen |
| 1997 | DATE | A gridless multi-layer router for standard cell circuits using CTM cells. | Hsiao-Ping Tseng, Carl Sechen |
| 1996 | ICCD | Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. | Bingzhong Guan, Carl Sechen |
| 1996 | ICCD | Clock-Delayed Domino for Adder and Combinational Logic Desig. | Gin Yee, Carl Sechen |
| 1995 | DAC | A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. | Ted Stanion, Carl Sechen |
| 1995 | DAC | Timing Driven Placement for Large Standard Cell Circuits. | William Swartz, Carl Sechen |
| 1995 | FPGA | Multiple FPGA Partitioning with Performance Optimization. | Kalapi Roy-Neogi, Carl Sechen |
| 1995 | ISCAS | Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. | Jer-Jaw Hsu, Carl Sechen |
| 1995 | ISCAS | Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. | Qicheng Yu, Carl Sechen |
| 1994 | ICCAD | A loosely coupled parallel algorithm for standard cell placement. | Wern-Jieh Sun, Carl Sechen |
| 1994 | ICCAD | Approximate symbolic analysis of large analog integrated circuits. | Qicheng Yu, Carl Sechen |
| 1994 | VLSID | A Sea-of-Gates Style FPGA Placement Algorithm. | Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen |
| 1993 | ICCAD | Maximum projections of don't care conditions in a Boolean network. | Ted Stanion, Carl Sechen |
| 1993 | ICCAD | Efficient and effective placement for very large circuits. | Wern-Jieh Sun, Carl Sechen |
| 1993 | ICCAD | A new generalized row-based global router. | William Swartz, Carl Sechen |
| 1990 | ICCAD | New Algorithms for the Placement and Routing of Macro Cells. | William Swartz, Carl Sechen |
| 1988 | DAC | Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. | Carl Sechen |
| 1988 | ICCAD | A new global router for row-based layout. | Kai-Win Lee, Carl Sechen |
| 1988 | ICCAD | An improved objective function for mincut circuit partitioning. | Carl Sechen, Dahe Chen |
| 1986 | DAC | TimberWolf3.2: a new standard cell placement and global routing package. | Carl Sechen, Alberto L. Sangiovanni-Vincentelli |