| 2023 | Tencon | Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis. | Dinesh Bhatia, Henrik Hesse |
| 2022 | VLSID | Robust Estimation of FPGA Resources and Performance from CNN Models. | Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia |
| 2021 | VLSID | An Automated Tool for Implementing Deep Neural Networks on FPGA. | Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia |
| 2020 | FPGA | MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. | Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia |
| 2017 | BSN | Portable impedance measurement device for sweat based glucose detection. | Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad |
| 2016 | FPGA | Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). | Pingakshya Goswami, Dinesh Bhatia |
| 2008 | FPL | A dynamic temperature control simulation system for FPGAs. | Shilpa Bhoj, Dinesh Bhatia |
| 2008 | ICCD | Early stage FPGA interconnect leakage power estimation. | Shilpa Bhoj, Dinesh Bhatia |
| 2007 | FPL | Pre-route Interconnect Capacitance and Power Estimation in FPGAs. | Shilpa Bhoj, Dinesh Bhatia |
| 2007 | ISCAS | Thermal Modeling and Temperature Driven Placement for FPGAs. | Shilpa Bhoj, Dinesh Bhatia |
| 2006 | VLSID | Exploring Logic Block Granularity in Leakage Tolerant FPGA. | Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara |
| 2005 | ASPDAC | Exploiting temporal idleness to reduce leakage power in programmable architectures. | Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia |
| 2005 | FPL | Timing Aware Interconnect Prediction Models for FPGAs. | Shankar Balachandran, Dinesh Bhatia |
| 2005 | VLSID | Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. | R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia |
| 2004 | VLSID | Estimating Pre-Placement FPGA Interconnection Requirements. | PariVallal Kannan, Dinesh Bhatia |
| 2003 | ICCD | Interconnect Estimation for FPGAs under Timing Driven Domains. | PariVallal Kannan, Dinesh Bhatia |
| 2002 | DAC | On metrics for comparing routability estimation methods for FPGAs. | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia |
| 2002 | FPL | Rapid and Reliable Routability Estimation for FPGAs. | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia |
| 2002 | VLSID | On Routing Demand and Congestion Estimation for FPGAs. | Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia |
| 2001 | FPL | Tightly Integrated Placement and Routing for FPGAs. | PariVallal Kannan, Dinesh Bhatia |
| 2001 | FPL | fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia |
| 1999 | FPGA | A Methodology for Fast FPGA Floorplanning. | John Marty Emmert, Dinesh Bhatia |
| 1999 | FPL | NEBULA: A Partially and Dynamically Reconfigurable Architecture. | Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan |
| 1999 | FPL | Tabu Search: Ultra-Fast Placement for FPGAs. | John Marty Emmert, Dinesh Bhatia |
| 1999 | ISCAS | Fast timing driven placement using tabu search. | John Marty Emmert, Dinesh Bhatia |
| 1999 | ISCAS | Clustering to improve bi-partition quality and run time. | Gregory Tumbush, Dinesh Bhatia |
| 1998 | FCCM | Temporal Partitioning and Scheduling for Reconfigurable Computing. | Karthikeya M. Gajjala Purna, Dinesh Bhatia |
| 1998 | FPL | REACT: Reactive Environment for Runtime Reconfiguration. | Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna |
| 1998 | FPL | Fast Floorplanning for FPGAs. | John Marty Emmert, Akash Randhar, Dinesh Bhatia |
| 1998 | ICCD | Partitioning in time: a paradigm for reconfigurable computing. | Karthikeya M. Gajjala Purna, Dinesh Bhatia |
| 1998 | ICCD | Clock-skew constrained placement for row based designs. | Natesan Venkateswaran, Dinesh Bhatia |
| 1998 | VLSID | Timing Driven Multi-FPGA Board Partitioning. | Raghu Burra, Dinesh Bhatia |
| 1998 | RSP | Emulating Large Designs on Small Reconfigurable Hardware. | Karthikeya M. Gajjala Purna, Dinesh Bhatia |
| 1997 | ASPDAC | A constructive method for data path area estimation during high-level VLSI synthesis. | Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri |
| 1997 | FPGA | Performance Driven Floorplanning for FPGA Based Designs. | Jianzhong Shi, Dinesh Bhatia |
| 1997 | FPL | Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. | John Marty Emmert, Dinesh Bhatia |
| 1997 | ICCD | Partitioning Under Timing and Area Constraints. | Gregory Tumbush, Dinesh Bhatia |
| 1997 | VLSID | Reconfigurable Computing. | Dinesh Bhatia |
| 1997 | VLSID | Macro Block Based FPGA Floorplanning. | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
| 1996 | FPL | RACE: Reconfigurable and Adaptive Computing Environment. | Doug Smith, Dinesh Bhatia |
| 1996 | ICCD | Multiway Partitioner for High Performance FPGA Based Board Architecture. | Vijayanand Sankarasubramanian, Dinesh Bhatia |
| 1996 | VLSID | Clock-Skew Constrained Cell Placement. | Natesan Venkateswaran, Dinesh Bhatia |
| 1995 | VLSID | Resource requirements for field programmable interconnection chips. | Dinesh Bhatia, James Haralambides |
| 1994 | VLSID | Hierarchical Reconfiguration of VLSI/WSI Arrays. | Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori |
| 1994 | VLSID | Detailed Routing of Multi-Terminal Nets in FPGAs. | Amit Chowdhary, Dinesh Bhatia |
| 1993 | ICCD | Pseudoexhaustive BIST for Sequential Circuits. | Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia |
| 1992 | WG | Improved Algorithms for Routing on Two-Dimensional Grids. | Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton |