| 2016 | DSD | Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. | Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Zouha Cherif, Maminionja Ravoson, Saqib Khan, Habib Mehrez |
| 2016 | PDP | Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. | Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid |
| 2016 | RSP | Inter-FPGA routing environment for performance exploration of multi-FPGA systems. | Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez |
| 2014 | ATSIP | MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. | Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez |
| 2014 | FCCM | Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. | Qingshan Tang, Matthieu Tuna, Habib Mehrez |
| 2014 | FPGA | Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). | Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang |
| 2014 | FPGA | Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only). | Qingshan Tang, Matthieu Tuna, Habib Mehrez |
| 2014 | FPL | Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. | Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez |
| 2014 | FPL | Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. | Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri |
| 2014 | ISCAS | Low-power comb decimation filter for RF Sigma-Delta ADCs. | Alp Kili, Delaram Haghighitalab, Habib Mehrez, Hassan Aboushady |
| 2013 | RSP | Routing algorithm for multi-FPGA based systems using multi-point physical tracks. | Qingshan Tang, Matthieu Tuna, Habib Mehrez |
| 2012 | RSP | Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. | Qingshan Tang, Habib Mehrez, Matthieu Tuna |
| 2010 | FPGA | Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). | Husain Parvez, Zied Marrakchi, Habib Mehrez |
| 2006 | FPGA | A multilevel hierarchical interconnection structure for FPGA. | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
| 2006 | FPGA | Configuration tools for a new multilevel hierarchical FPGA. | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
| 2006 | ICCAD | Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
| 2001 | ISCAS | Customizable DSP architecture for ASIP core design. | Yann Bajot, Habib Mehrez |
| 2001 | ISCAS | A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. | Yannick Dumonteix, Yann Bajot, Habib Mehrez |
| 2000 | ISCAS | A family of redundant multipliers dedicated to fast computation for signal processing. | Yannick Dumonteix, Habib Mehrez |
| 1995 | ARITH | Application of fast layout synthesis environment to dividers evaluation. | A. Houelle, Habib Mehrez, Nicolas Vaucher, Luis A. Montalvo, Alain Guyot |
| 1995 | VLSID | Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. | Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher |