Haile Yu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2008–2012
Best venue rank
B
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ASPDAC | CODA: A concurrent online delay measurement architecture for critical paths. | Yubin Zhang, Haile Yu, Qiang Xu |
| 2011 | FPGA | On timing yield improvement for FPGA designs using architectural symmetry (abstract only). | Haile Yu, Qiang Xu, Philip Heng Wai Leong |
| 2011 | FPL | On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. | Haile Yu, Qiang Xu, Philip Heng Wai Leong |
| 2009 | FPL | Towards a unique FPGA-based identification circuit using process variations. | Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Mller, Manfred Glesner, Peter Zipf |
| 2008 | FPGA | FPGA interconnect design using logical effort. | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |
| 2008 | FPL | FPGA interconnect sizing using extended logical effort model. | Haile Yu |
| 2008 | FPL | FPGA interconnect design using logical effort. | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |