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Hans G. Kerkhoff

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

66

Venues

11

Active years

1988–2021

Best venue rank

B

Where they publish

Papers

66 indexed papers, newest first.

YearVenueTitleAuthors
2021DDECSEmbedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level.Hassan Ebrahimi, Hans G. Kerkhoff
2020ETSA New Monitor Insertion Algorithm for Intermittent Fault Detection.Hassan Ebrahimi, Hans G. Kerkhoff
2020IOLTSLife-Time Prognostics of Dependable VLSI-SoCs using Machine-learning.Leila Bagheriye, Ghazanfar Ali, Hans G. Kerkhoff
2020ISCASOn-Chip Embedded Instruments Data Fusion and Life-Time Prognostics of Dependable VLSI-SoCs using Machine-Learning.Ghazanfar Ali, Leila Bagheriye, Hans G. Kerkhoff
2019ETSIJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation.Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff
2019ITCDARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips.Ahmed M. Y. Ibrahim, Hans G. Kerkhoff
2019VTSEfficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks.Ahmed M. Y. Ibrahim, Hans G. Kerkhoff, Abrar Ibrahim, Mona Safar, M. Watheq El-Kharashi
2018DDECSIntermittent Resistance Fault Detection at Board Level.Hassan Ebrahimi, Hans G. Kerkhoff
2017DATEBASTION: Board and SoC test instrumentation for ageing and no failure found.Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2017ETSImproving the dependability of AMR sensors used in automotive applications.Andreina Zambrano, Hans G. Kerkhoff
2017IOLTSA cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687.Ahmed Ibrahim, Hans G. Kerkhoff
2017VTSStructured scan patterns retargeting for dynamic instruments access.Ahmed Ibrahim, Hans G. Kerkhoff
2016DSDTesting for Intermittent Resistive Faults in CMOS Integrated Systems.Hassan Ebrahimi, Hans G. Kerkhoff
2016ETSAnalysis and design of an on-chip retargeting engine for IEEE 1687 networks.Ahmed Ibrahim, Hans G. Kerkhoff
2016FDLDesigning reliable cyber-physical systems overview associated to the special session at FDL'16.Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Grschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Knighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Rck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016IOLTSOnline monitoring of the maximum angle error in AMR sensors.Andreina Zambrano, Hans G. Kerkhoff
2016VTSThermal issues in test: An overview of the significant aspects and industrial practice.Juergen Alt, Paolo Bernardi, Alberto Bosio, Riccardo Cantoro, Hans G. Kerkhoff, Andreas Leininger, Wolfgang Molzer, Alessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, R. Strasser
2015DDECSIntermittent Resistive Faults in Digital CMOS Circuits.Hans G. Kerkhoff, Hassan Ebrahimi
2015DSDUnit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor.Yong Zhao, Hans G. Kerkhoff
2015ETSNew drain current model for nano-meter MOS transistors on-chip threshold voltage test.Jinbo Wan, Hans G. Kerkhoff
2015IOLTSOn the maximization of the sustained switching activity in a processor.Riccardo Cantoro, Matteo Sonza Reorda, Alireza Rohani, Hans G. Kerkhoff
2015IOLTSFault-tolerant system for catastrophic faults in AMR sensors.Andreina Zambrano, Hans G. Kerkhoff
2014DATEAn embedded offset and gain instrument for OpAmp IPs.Jinbo Wan, Hans G. Kerkhoff
2014DDECSStudying DAC capacitor-array degradation in charge-redistribution SAR ADCs.Muhammad Aamir Khan, Hans G. Kerkhoff
2014DSDDesign of an Embedded Health Monitoring Infrastructure for Accessing Multi-processor SoC Degradation.Yong Zhao, Hans G. Kerkhoff
2014ETSTwo soft-error mitigation techniques for functional units of DSP processors.Alireza Rohani, Hans G. Kerkhoff
2013DDECSAn indirect technique for estimating reliability of analog and mixed-signal systems during operational life.Muhammad Aamir Khan, Hans G. Kerkhoff
2013DSDThe Essence of Reliability Estimation during Operational Life for Achieving High System Dependability.Muhammad Aamir Khan, Hans G. Kerkhoff
2012DATEMonitoring active filters under automotive aging scenarios with embedded instrument.Jinbo Wan, Hans G. Kerkhoff
2012DDECSThe design of dependable flexible multi-sensory System-on-Chips for security applications.Hans G. Kerkhoff, Yong Zhao
2012DSDInvestigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design.Benaoumeur Senouci, Anne-Johan Annema, Mark J. Bentum, Hans G. Kerkhoff
2012ETSA robust metric for screening outliers from analogue product manufacturing tests responses.Shaji Krishnan, Hans G. Kerkhoff
2011DDECSA system-level platform for dependability enhancement and its analysis for mixed-signal SoCs.Muhammad Aamir Khan, Hans G. Kerkhoff
2011DSDA Technique for Accelerating Injection of Transient Faults in Complex SoCs.Alireza Rohani, Hans G. Kerkhoff
2011DSNStudy of the effects of SET induced faults on submicron technologies.Alireza Rohani, Hans G. Kerkhoff
2011ETSA Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests Responses.Shaji Krishnan, Hans G. Kerkhoff
2011PRDCA Dependability Solution for Homogeneous MPSoCs.Xiao Zhang, Hans G. Kerkhoff
2010DATEBlock-level bayesian diagnosis of analogue electronic circuits.Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, Hans G. Kerkhoff
2010DSDOn-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism.Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
2010ETSMultivariate model for test response analysis.Shaji Krishnan, Hans G. Kerkhoff
2010ETSPredicting dynamic specifications of ADCs with a low-quality digital input signal.Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff
2010ETSNew scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism.Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
2009DSDDesign of a Highly Dependable Beamforming Chip.Xiao Zhang, Hans G. Kerkhoff
2009ETSAlgorithms for ADC Multi-site Test with Digital Input Stimulus.Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud
2005ETSTesting of MEMS-based microsystems.Hans G. Kerkhoff
2003ETSScan test strategy for asynchronous-synchronous interfaces [SoC testing].Octavian Petre, Hans G. Kerkhoff
2003ETSEnhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores.H. J. Vermaak, Hans G. Kerkhoff
2003ITCTowards Structural Testing of Superconductor Electronics.Arun A. Joseph, Hans G. Kerkhoff
2003VTSTestable Design and Testing of Micro-Electro-Fluidic Arrays.Hans G. Kerkhoff, Mustafa Acar
2002ITCAutomatic Scan Insertion and Test Generation for Asynchronous Circuits.Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff
2002ITCA New Test Generation Approach for Embedded Analogue Cores in SoC.M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff
2002VTSSoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
2001ETSReducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design.Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff
2001ETSReducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations.Herman J. Vermaak, Hans G. Kerkhoff
2001ETSAn implementation for test-time reduction in VLIW transport-triggered architectures.V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff
2001IOLTSIncreasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.Octavian Petre, Hans G. Kerkhoff
2001ITCTackling test trade-offs from design, manufacturing to market using economic modeling.Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff
2000DATEDesign and Test Space Exploration of Transport-Triggered Architectures.V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff
2000ETSBridging the testing speed gap: design for delay testability.Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani
2000VTSA Low-Speed BIST Framework for High-Performance Circuit Testing.Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
1997DATECompact structural test generation for analog macros.V. Kaal, Hans G. Kerkhoff
1997DATESmart sensor system application: an integrated compass.Ronald J. W. T. Tangelder, G. Diemel, Hans G. Kerkhoff
1996DATETest Structures on MCM Active Substrate: Is it worthwhile?Joan Oliver, Hans G. Kerkhoff
1995DATEGate delay fault test generation for non-scan circuits.G. Van Brakel, Uwe Glser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus
1991VTSA design-for-testability expert system for silicon compilers.R. P. van Riessen, Hans G. Kerkhoff, J. M. J. Janssen
1988ITCTASTE: A Tool for Analog System Testability Evaluation.Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff