| 1998 | VLSID | Optimizing Logic Design Using Boolean Transforms. | Pramit Chavda, James Jacob, Vishwani D. Agrawal |
| 1998 | VLSID | A Fast Two-level Logic Minimizer. | P. Srinivasa Rao, James Jacob |
| 1997 | VLSID | Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. | James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal |
| 1996 | ICIP | Lossless Compression Of Images Using Logic Minimization. | Anil K. Chaudhay, Jacob Augustine, James Jacob |
| 1996 | VLSID | Cubical CAMP for minimization of Boolean functions. | Nripendra N. Biswas, C. Srikanth, James Jacob |
| 1996 | VLSID | On test coverage of path delay faults. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1995 | VLSID | Logic minimization based approach for compressing image data. | Jacob Augustine, Wen Feng, James Jacob |
| 1995 | VLSID | An efficient automatic test generation system for path delay faults in combinational circuits. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1995 | VLSID | Functional test generation for non-scan sequential circuits. | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
| 1994 | VLSID | An Improved Deductive Fault Simulator. | P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal |
| 1993 | VLSID | Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. | P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob |
| 1992 | VLSID | Functional Test Generation for Sequential Circuits. | James Jacob, Vishwani D. Agrawal |
| 1992 | VLSID | An Efficient Rule Based Fault Simulator. | Oommen Tharakan, James Jacob, Mandyam-Komar Srinivas |
| 1985 | ITC | : A Testable PLA Design with Minimal Hardware and Test Set. | James Jacob, Nripendra N. Biswas |