| 2026 | DATE | Entropy Sampling-Based Neural Architecture Search for Resource-Constrained Microcontroller Targets. | Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jrgen Teich |
| 2026 | DATE | Multi-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAI. | Georgios Sotiropoulos, Felix Frombach, Julian Hfer, Tanja Harbaum, Jrgen Becker, Henrik Iver Thore, Vincent Meyers, Mehdi B. Tahoori, Zeynep Demirdag, Mohammed Bakr Sikal, Hassan Nassar, Heba Khdr, Jrg Henkel, Christopher Wolters, Philipp van Kempen, Johannes Geier, Ulf Schlichtmann, Batuhan Sesli, Muhammad Sabih, Jakob Wittmann, Frank Hannig, Jrgen Teich, Lukas Steiner, Norbert Wehn, Mohamed Shelkamy Ali, Philipp Schmitz, Wolfgang Kunz, Stefan Koegler, Georg Sigl |
| 2025 | ASPDAC | Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2025 | BTW | ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. | Tobias Hahn, Maximilian S. Langohr, Stefan Meiner, Benedikt Dring, Stefan Wildermann, Klaus Meyer-Wegener, Jrgen Teich |
| 2025 | DATE | Co-Design of Sustainable Embedded Systems-on-Chip. | Jan Spieck, Dominik Walter, Jan Waschkeit, Jrgen Teich |
| 2025 | DATE | Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). | Mehdi B. Tahoori, Jrgen Becker, Jrg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jrgen Teich, Norbert Wehn |
| 2025 | EWSN | WiP Paper: Utility-Aware Transmission of Sensor Data on Energy-Harvesting IoT Gateways. | Pierre-Louis Sixdenier, Jebacyril Arockiaraj, Stefan Wildermann, Jrgen Teich |
| 2025 | GECCO | Multi-Objective Bayesian Optimization with Reinforcement Learning for Edge Deployment of DNNs on Microcontrollers. | Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jrgen Teich |
| 2025 | ICCAD | Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. | Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2024 | DATE | Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2024 | DATE | Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. | Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jrgen Teich |
| 2024 | DDECS | ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. | Tobias Hahn, Daniel Schll, Stefan Wildermann, Jrgen Teich |
| 2024 | DSD | DSL-Based SNN Accelerator Design Using Chisel. | Patrick Plagwitz, Frank Hannig, Jrgen Teich, Oliver Keszcze |
| 2024 | FPL | JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2024 | ISCAS | ALPACA: An Accelerator Chip for Nested Loop Programs. | Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2024 | MEMOCODE | Self-Powering Dataflow Networks - Concepts and Implementation. | Abrarul Karim, Joachim Falk, Dennis Schmidt, Jrgen Teich |
| 2024 | VEHITS | Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. | Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jrgen Teich |
| 2023 | BTW | An FPGA Avro Parser Generator for Accelerated Data Stream Processing. | Tobias Hahn, Daniel Schll, Stefan Wildermann, Jrgen Teich |
| 2023 | CASES | Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. | Jrg Henkel, Lokesh Siddhu, Lars Bauer, Jrgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jernimo Castrilln, Asif Ali Khan, Hamid Farzaneh, Joo Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng |
| 2023 | EuroSys | Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. | Muhammad Sabih, Mikail Yayla, Frank Hannig, Jrgen Teich, Jian-Jia Chen |
| 2023 | FPL | SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2023 | MEMOCODE | Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. | Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2022 | CCS | Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. | Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2022 | DATE | Raw Filtering of JSON Data on FPGAs. | Tobias Hahn, Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2022 | EuroSys | DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. | Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2022 | FCCM | Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. | Jens Trautmann, Jrgen Teich, Stefan Wildermann |
| 2022 | FPL | Real-Time Waveform Matching with a Digitizer at 10 GS/s. | Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jrgen Teich, Stefan Wildermann |
| 2022 | FPL | Auto-Tuning of Raw Filters for FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2022 | FPL | TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. | Patrick Plagwitz, Frank Hannig, Jrgen Teich |
| 2022 | FPL | DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. | Jan Sommer, M. Akif zkan, Oliver Keszcze, Jrgen Teich |
| 2022 | IWCMC | Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. | Peter Brand, Benjamin Hackenberg, Joachim Falk, Jrgen Teich |
| 2021 | DATE | Approximate Logic Synthesis of Very Large Boolean Networks. | Jorge Echavarria, Stefan Wildermann, Jrgen Teich |
| 2021 | DSN | Fault-Tolerant Low-Precision DNNs using Explainable AI. | Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2021 | ETS | Emerging Computing Devices: Challenges and Opportunities for Test and Reliability | Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jrgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels |
| 2021 | FCCM | A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. | Patrick Plagwitz, Frank Hannig, Martin Strbel, Christoph Strohmeyer, Jrgen Teich |
| 2021 | FPL | Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. | Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jrgen Teich |
| 2021 | FPL | Choice - A Tunable PUF-Design for FPGAs. | Franz-Josef Streit, Paul Krger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jrgen Teich |
| 2021 | ICCAD | Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. | Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jrgen Teich, Ian O'Connor |
| 2021 | ISNCC | Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. | Peter Brand, Joachim Falk, Eduard Potwigin, Jrgen Teich |
| 2021 | MEMOCODE | Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2021 | MEMOCODE | LION: real-time I/O transfer control for massively parallel processor arrays. | Dominik Walter, Jrgen Teich |
| 2021 | SAC | Aarith: an arbitrary precision number library. | Oliver Keszcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jrgen Teich |
| 2021 | SCOPES | Efficient Application of Tensor Core Units for Convolving Images. | Stefan Groth, Jrgen Teich, Frank Hannig |
| 2020 | ASPDAC | Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. | Jrgen Teich, Behnaz Pourmohseni, Oliver Keszcze, Jan Spieck, Stefan Wildermann |
| 2020 | DAC | Probabilistic Error Propagation through Approximated Boolean Networks. | Jorge Echavarria, Stefan Wildermann, Oliver Keszcze, Jrgen Teich |
| 2020 | DAC | The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. | Bo Qiao, M. Akif zkan, Jrgen Teich, Frank Hannig |
| 2020 | DAC | Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. | Jan Spieck, Stefan Wildermann, Jrgen Teich |
| 2020 | DATE | Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. | Fedor Smirnov, Behnaz Pourmohseni, Jrgen Teich |
| 2020 | EDBT | SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. | Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jrgen Teich |
| 2020 | EuroPar | HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. | Samer Alhaddad, Jens Frstner, Stefan Groth, Daniel Grnewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jrgen Teich, Martin Weiser, Florian Wende |
| 2020 | MEMOCODE | Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. | Dominik Walter, Michael Witterauf, Jrgen Teich |
| 2020 | PPoPP | Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. | Bo Qiao, Oliver Reiche, Jrgen Teich, Frank Hannig |
| 2020 | WCNC | Clustering-Based Scenario-Aware LTE Grant Prediction. | Peter Brand, Muhammad Sabih, Joachim Falk, Jonathan Ah Sue, Jrgen Teich |
| 2020 | SCOPES | Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. | Christian Heidorn, Frank Hannig, Jrgen Teich |
| 2020 | SCOPES | Efficient parallel reduction on GPUs with Hipacc. | Bo Qiao, Oliver Reiche, M. Akif zkan, Jrgen Teich, Frank Hannig |
| 2019 | BTW | ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. | Andreas Becher, Achim Herrmann, Stefan Wildermann, Jrgen Teich |
| 2019 | CGO | From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. | Bo Qiao, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2019 | DaMoN | In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. | Andreas Becher, Jrgen Teich |
| 2019 | DSN | Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures. | Hananeh Aliee, Faramarz Khosravi, Jrgen Teich |
| 2019 | ECRTS | Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. | Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jrgen Teich |
| 2019 | HCI | Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and Its Application to Mobile Devices. | Jonathan Ah Sue, Peter Brand, Joachim Falk, Ralph Hasholzner, Jrgen Teich |
| 2019 | MEMOCODE | Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2019 | RTSS | Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. | Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jrgen Teich, Jrg Henkel |
| 2019 | SCOPES | SYCL Code Generation for Multigrid Methods. | Stefan Groth, Christian Schmitt, Jrgen Teich, Frank Hannig |
| 2019 | SCOPES | On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures. | Martn Letras, Joachim Falk, Tobias Schwarzer, Jrgen Teich |
| 2019 | VEHITS | Variety-aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks. | Fedor Smirnov, Behnaz Pourmohseni, Michael Gla, Jrgen Teich |
| 2018 | CEC | Probabilistic Dominance in Robust Multi-Objective Optimization. | Faramarz Khosravi, Michael Borst, Jrgen Teich |
| 2018 | DAC | Architecture decomposition in system synthesis of heterogeneous many-core systems. | Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jrgen Teich, Michael Gla |
| 2018 | DaMoN | Optimistic regular expression matching on FPGAs for near-data processing. | Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2018 | DATE | Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. | Jrg Fickenscher, Jens Schlumberger, Frank Hannig, Jrgen Teich, Mohamed Essayed Bouzouraa |
| 2018 | ICCAD | Design space exploration of multi-output logic function approximations. | Jorge Echavarria, Stefan Wildermann, Jrgen Teich |
| 2018 | ICCAD | Dynamic resource management for heterogeneous many-cores. | Jrg Henkel, Jrgen Teich, Stefan Wildermann, Hussam Amrouch |
| 2018 | MEMOCODE | Run-time Requirement Enforcement for Loop Programs on Processor Arrays. | Michael Witterauf, Jrgen Teich |
| 2018 | WCNC | A predictive dynamic power management for LTE-Advanced mobile devices. | Jonathan Ah Sue, Peter Brand, Johannes Brendel, Ralph Hasholzner, Joachim Falk, Jrgen Teich |
| 2018 | SCOPES | Reinforcement Learning for Power-Efficient Grant Prediction in LTE. | Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jrgen Teich |
| 2018 | SCOPES | Automatic Kernel Fusion for Image Processing DSLs. | Bo Qiao, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2018 | SCOPES | Automatic Optimization of Redundant Message Routings in Automotive Networks. | Fedor Smirnov, Felix Reimann, Jrgen Teich, Zhao Han, Michael Gla |
| 2018 | VEHITS | Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. | Jrg Fickenscher, Frank Hannig, Jrgen Teich, Mohamed Essayed Bouzouraa |
| 2017 | DAC | Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks. | Fedor Smirnov, Michael Gla, Felix Reimann, Jrgen Teich |
| 2017 | DATE | Automatic operating point distillation for hybrid mapping methodologies. | Behnaz Pourmohseni, Michael Gla, Jrgen Teich |
| 2017 | DATE | Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks. | Fedor Smirnov, Michael Gla, Felix Reimann, Jrgen Teich |
| 2017 | ICCAD | Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). | Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jrgen Teich, Frank Hannig |
| 2017 | RSP | Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2017 | RTNS | Predictable run-time mapping reconfiguration for real-time applications on many-core systems. | Behnaz Pourmohseni, Stefan Wildermann, Michael Gla, Jrgen Teich |
| 2017 | SCOPES | Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. | Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jrgen Teich, Stefan Wildermann |
| 2017 | SCOPES | Automatic Conversion of Simulink Models to SysteMoC Actor Networks. | Martn Letras, Joachim Falk, Stefan Wildermann, Jrgen Teich |
| 2017 | SCOPES | Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. | Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jrgen Teich, Stefan Wildermann |
| 2016 | DAC | Formal reliability analysis of switched ethernet automotive networks under transient transmission errors. | Fedor Smirnov, Michael Gla, Felix Reimann, Jrgen Teich |
| 2016 | ETFA | A heterogeneous multi-core SoC for mixed criticality industrial automation systems. | Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jrgen Teich |
| 2016 | FCCM | A LUT-Based Approximate Adder. | Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jrgen Teich |
| 2016 | FPL | FPGA-based accelerator design from a domain-specific language. | M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2016 | PCS | Multi-objective design space exploration for the optimization of the HEVC mode decision process. | Christian Herglotz, Rafael Rosales, Michael Gla, Jrgen Teich, Andr Kaup |
| 2016 | PLDI | ActorX10: an actor library for X10. | Sascha Roloff, Alexander Pppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Gla, Frank Hannig, Jrgen Teich |
| 2016 | SCOPES | Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. | Andreas Weichslgartner, Stefan Wildermann, Johannes Gtzfried, Felix C. Freiling, Michael Gla, Jrgen Teich |
| 2015 | DAC | Robust design of E/E architecture component platforms. | Sebastian Graf, Sebastian Reinhart, Michael Gla, Jrgen Teich, Daniel Platte |
| 2015 | DAC | Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. | Sascha Roloff, David Schafhauser, Frank Hannig, Jrgen Teich |
| 2015 | DATE | Uncertainty-aware reliability analysis and optimization. | Faramarz Khosravi, Malte Mller, Michael Gla, Jrgen Teich |
| 2015 | DATE | Formal analysis of the startup delay of SOME/IP service discovery. | Jan R. Seyler, Thilo Streichert, Michael Gla, Nicolas Navet, Jrgen Teich |
| 2015 | ISORC | Design Methodology and Run-Time Management for Predictable Many-Core Systems. | Stefan Wildermann, Andreas Weichslgartner, Jrgen Teich |
| 2015 | MEMOCODE | Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |
| 2015 | SCOPES | Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling. | Tobias Schwarzer, Joachim Falk, Michael Gla, Jrgen Teich, Christian Zebelein, Christian Haubelt |
| 2015 | SCOPES | Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. | ricles Sousa, Frank Hannig, Jrgen Teich, Qingqing Chen, Ulf Schlichtmann |
| 2015 | SCOPES | Adaptive Isolation for Predictable MPSoC Stream Processing. | Jrgen Teich |
| 2014 | ACSSC | Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. | Deepak Gangadharan, ricles Sousa, Vahid Lari, Frank Hannig, Jrgen Teich |
| 2014 | DAC | CAP: Communication Aware Programming. | Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jrgen Teich, Jrg Henkel, Gregor Snelting, Andreas Herkersdorf, Jrgen Becker |
| 2014 | DAC | Multi-Objective Local-Search Optimization using Reliability Importance Measuring. | Faramarz Khosravi, Felix Reimann, Michael Gla, Jrgen Teich |
| 2014 | DAC | Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. | Felix Reimann, Michael Gla, Jrgen Teich, Alejandro Cook, Laura Rodrguez Gmez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein |
| 2014 | DATE | Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. | Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Gla, Felix Reimann, Laura Rodrguez Gmez, Thomas Russ, Jrgen Teich, Dominik Ull, Hans-Joachim Wunderlich |
| 2014 | DATE | Multi-variant-based design space exploration for automotive embedded systems. | Sebastian Graf, Michael Gla, Jrgen Teich, Christoph Lauer |
| 2014 | DATE | Code generation for embedded heterogeneous architectures on android. | Richard Membarth, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2014 | DATE | A self-propagating wakeup mechanism for point-to-point networks with partial network support. | Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spagele, Michael Gla, Jrgen Teich |
| 2014 | DATE | Multi-objective distributed run-time resource management for many-cores. | Stefan Wildermann, Michael Gla, Jrgen Teich |
| 2014 | DATE | Model-based actor multiplexing with application to complex communication protocols. | Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jrgen Teich |
| 2014 | DSD | Design Space Exploration for Automotive E/E Architecture Component Platforms. | Sebastian Graf, Michael Gla, Jrgen Teich, Christoph Lauer |
| 2014 | DSD | Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. | ricles Sousa, Deepak Gangadharan, Frank Hannig, Jrgen Teich |
| 2014 | DSD | Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems. | Liyuan Zhang, Joachim Falk, Tobias Schwarzer, Michael Gla, Jrgen Teich |
| 2014 | EuroPar | ExaStencils: Advanced Stencil-Code Engineering. | Christian Lengauer, Sven Apel, Matthias Bolten, Armin Grlinger, Frank Hannig, Harald Kstler, Ulrich Rde, Jrgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt |
| 2014 | FCCM | A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. | Robrt Glein, Bernhard Schmidt, Florian Rittner, Jrgen Teich, Daniel Ziener |
| 2014 | FPGA | An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). | Bernhard Schmidt, Daniel Ziener, Jrgen Teich |
| 2014 | FPL | Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. | Andreas Becher, Florian Bauer, Daniel Ziener, Jrgen Teich |
| 2014 | FPL | An image processing library for C-based high-level synthesis. | Moritz Schmid, Nicolas Apelt, Frank Hannig, Jrgen Teich |
| 2014 | ICCSA | An Evaluation of Domain-Specific Language Technologies for Code Generation. | Christian Schmitt, Sebastian Kuckuk, Harald Kstler, Frank Hannig, Jrgen Teich |
| 2014 | MEMOCODE | Symbolic inner loop parallelisation for massively parallel processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |
| 2014 | SC | ExaSlang: a domain-specific language for highly scalable multigrid solvers. | Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Kstler, Jrgen Teich |
| 2013 | DAC | On robust task-accurate performance estimation. | Yang Xu, Bo Wang, Ralph Hasholzner, Rafael Rosales, Jrgen Teich |
| 2013 | DATE | Automatic success tree-based reliability analysis for the consideration of transient and permanent faults. | Hananeh Aliee, Michael Gla, Felix Reimann, Jrgen Teich |
| 2013 | DATE | Game-theoretic analysis of decentralized core allocation schemes on many-core systems. | Stefan Wildermann, Tobias Ziermann, Jrgen Teich |
| 2013 | DSD | AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. | Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jrgen Teich, Jrgen Becker, Andreas Herkersdorf |
| 2013 | ETFA | Timing analysis of Ethernet AVB-based automotive E/E architectures. | Felix Reimann, Sebastian Graf, Fabian Streit, Michael Gla, Jrgen Teich |
| 2013 | FCCM | Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. | Christopher Dennl, Daniel Ziener, Jrgen Teich |
| 2013 | FDL | Representing mapping and scheduling decisions within dataflow graphs. | Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jrgen Teich |
| 2013 | FDL | Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation. | Liyuan Zhang, Michael Gla, Nils Ballmann, Jrgen Teich |
| 2013 | SCOPES | NoC simulation in heterogeneous architectures for PGAS programming model. | Sascha Roloff, Andreas Weichslgartner, Jan Heiwolf, Frank Hannig, Jrgen Teich |
| 2012 | ASPDAC | Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. | Sascha Roloff, Frank Hannig, Jrgen Teich |
| 2012 | DAC | Considering diagnosis functionality during automatic system-level design of automotive networks. | Michael Eberl, Michael Gla, Jrgen Teich, Ulrich Abelein |
| 2012 | DATE | Designing FlexRay-based automotive architectures: A holistic OEM approach. | Paul Milbredt, Michael Gla, Martin Lukasiewycz, Andreas Steininger, Jrgen Teich |
| 2012 | DATE | Variation-aware leakage power model extraction for system-level hierarchical power analysis. | Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jrgen Teich |
| 2012 | EuroPar | Mastering Software Variant Explosion for GPU Accelerators. | Richard Membarth, Frank Hannig, Jrgen Teich, Mario Krner, Wieland Eckert |
| 2012 | FCCM | On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. | Christopher Dennl, Daniel Ziener, Jrgen Teich |
| 2012 | FCCM | Power Management Strategies for Serial RapidIO Endpoints in FPGAs. | Moritz Schmid, Frank Hannig, Jrgen Teich |
| 2012 | FDL | Invasive computing - Concepts and overheads. | Jrgen Teich, Andreas Weichslgartner, Benjamin Oechslein, Wolfgang Schrder-Preikschat |
| 2012 | ISPDC | Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. | Richard Membarth, Frank Hannig, Jrgen Teich, Mario Krner, Wieland Eckert |
| 2012 | SC | Towards Domain-Specific Computing for Stencil Codes in HPC. | Richard Membarth, Frank Hannig, Jrgen Teich, Harald Kstler |
| 2012 | SAFECOMP | Cross-Level Compositional Reliability Analysis for Embedded Systems. | Michael Gla, Heng Yu, Felix Reimann, Jrgen Teich |
| 2012 | SCOPES | Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. | Sascha Roloff, Frank Hannig, Jrgen Teich |
| 2011 | ATC | Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems. | Tobias Ziermann, Zoran Salcic, Jrgen Teich |
| 2011 | DAC | Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks. | Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nbauer, Jrgen Teich |
| 2011 | DAC | Symbolic system synthesis in the presence of stringent real-time constraints. | Felix Reimann, Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2011 | DATE | A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. | Joachim Falk, Christian Zebelein, Christian Haubelt, Jrgen Teich |
| 2011 | DATE | An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). | Andreas Kern, Thilo Streichert, Jrgen Teich |
| 2011 | DATE | DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. | Tobias Ziermann, Jrgen Teich, Zoran Salcic |
| 2011 | FDL | ESL power and performance estimation for heterogeneous MPSOCS using SystemC. | Martin Streubhr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jrgen Teich |
| 2011 | FPL | Stress-Aware Module Placement on Reconfigurable Devices. | Josef Angermeier, Daniel Ziener, Michael Gla, Jrgen Teich |
| 2011 | FPL | Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. | Stefan Wildermann, Jrgen Teich, Daniel Ziener |
| 2011 | GECCO | Opt4J: a modular framework for meta-heuristic optimization. | Martin Lukasiewycz, Michael Gla, Felix Reimann, Jrgen Teich |
| 2011 | RSP | Automatic generation of system-level virtual prototypes from streaming application models. | Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jrgen Teich |
| 2011 | SCOPES | Resource-aware programming and simulation of MPSoC architectures through extension of X10. | Frank Hannig, Sascha Roloff, Gregor Snelting, Jrgen Teich, Andreas Zwinkau |
| 2010 | ATC | Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. | Stefan Wildermann, Andreas Oetken, Jrgen Teich, Zoran A. Salcic |
| 2010 | DAC | Towards scalable system-level reliability analysis. | Michael Gla, Martin Lukasiewycz, Christian Haubelt, Jrgen Teich |
| 2010 | DATE | Robust design of embedded systems. | Martin Lukasiewycz, Michael Gla, Jrgen Teich |
| 2010 | DATE | A rapid prototyping system for error-resilient multi-processor systems-on-chip. | Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jrgen Teich |
| 2010 | DATE | Efficient High-Level modeling in the networking domain. | Christian Zebelein, Joachim Falk, Christian Haubelt, Jrgen Teich, Rainer Dorsch |
| 2010 | EMSOFT | Model-based analysis, synthesis and testing of automotive hardware/software architectures. | Samarjit Chakraborty, S. Ramesh, Jrgen Teich |
| 2010 | EuroPar | Generating GPU Code from a High-Level Representation for Image Processing Kernels. | Richard Membarth, Anton Lokhmotov, Jrgen Teich |
| 2010 | FCCM | Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. | Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jrgen Teich |
| 2010 | FCCM | Using the Power Side Channel of FPGAs for Communication. | Daniel Ziener, Florian Baueregger, Jrgen Teich |
| 2010 | FPL | A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. | Andreas Oetken, Stefan Wildermann, Jrgen Teich, Dirk Koch |
| 2010 | ICCAD | Symbolic system level reliability analysis. | Michael Gla, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jrgen Teich |
| 2010 | ICCCN | Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems. | Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hbner, Jrgen Teich |
| 2010 | ISORC | A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. | Tobias Ziermann, Nina Mhleis, Stefan Wildermann, Jrgen Teich |
| 2009 | DAC | Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. | Michael Gla, Martin Lukasiewycz, Jrgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty |
| 2009 | DATE | Incorporating graceful degradation into embedded system design. | Michael Gla, Martin Lukasiewycz, Christian Haubelt, Jrgen Teich |
| 2009 | DATE | Model-based synthesis and optimization of static multi-rate image processing algorithms. | Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jrgen Teich |
| 2009 | DATE | Combined system synthesis and communication architecture exploration for MPSoCs. | Martin Lukasiewycz, Martin Streubhr, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2009 | DATE | CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16 higher data rates. | Tobias Ziermann, Stefan Wildermann, Jrgen Teich |
| 2009 | FCCM | Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. | Dirk Koch, Christian Beckhoff, Jrgen Teich |
| 2009 | FCCM | Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. | Joon Edward Sim, Weng-Fai Wong, Jrgen Teich |
| 2009 | FDL | Efficient approximately-timed performance modeling for architectural exploration of MPSoCs. | Martin Streubhr, Jens Gladigau, Christian Haubelt, Jrgen Teich |
| 2009 | FPGA | A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. | Dirk Koch, Christian Beckhoff, Jrgen Teich |
| 2009 | FPL | General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. | Josef Angermeier, Abdulazim Amouri, Jrgen Teich |
| 2009 | FPL | Self-organizing multi-cue fusion for FPGA-based embedded imaging. | Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jrgen Teich |
| 2008 | ASPDAC | Efficient symbolic multi-objective design space exploration. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2008 | ATC | Concepts for Autonomous Control Flow Checking for Embedded CPUs. | Daniel Ziener, Jrgen Teich |
| 2008 | CEC | A feasibility-preserving local search operator for constrained discrete optimization problems. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2008 | DAC | Concurrent topology and routing optimization in automotive network integration. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich, Richard Regler, Bardo Lang |
| 2008 | DATE | Symbolic Reliability Analysis and Optimization of ECU Networks. | Michael Gla, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jrgen Teich |
| 2008 | DSD | Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. | Rainer Schaffer, Renate Merker, Frank Hannig, Jrgen Teich |
| 2008 | DSD | Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | EMSOFT | A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. | Joachim Falk, Joachim Keinert, Christian Haubelt, Jrgen Teich, Shuvra S. Bhattacharyya |
| 2008 | FCCM | Efficient Reconfigurable On-Chip Buses for FPGAs. | Dirk Koch, Christian Haubelt, Jrgen Teich |
| 2008 | FCCM | Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | FDL | Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. | Jens Gladigau, Christian Haubelt, Jrgen Teich |
| 2008 | FDL | Symbolic Scheduling of SystemC Dataflow Designs. | Jens Gladigau, Christian Haubelt, Jrgen Teich |
| 2008 | FPL | Fine grain reconfigurable architectures. | Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker |
| 2008 | FPL | A comparison of embedded reconfigurable video-processing architectures. | Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jrgen Teich |
| 2008 | FPL | Coarse-grained reconfiguration. | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jrgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jrgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
| 2008 | FPL | No-break dynamic defragmentation of reconfigurable devices. | Sndor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jrgen Teich |
| 2008 | FPL | ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. | Dirk Koch, Christian Beckhoff, Jrgen Teich |
| 2008 | FPL | Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | HIS | A Sequential Learning Resource Allocation Network for Image Processing Applications. | Stefan Wildermann, Jrgen Teich |
| 2008 | MEMOCODE | Classification of General Data Flow Actors into Known Models of Computation. | Christian Zebelein, Joachim Falk, Christian Haubelt, Jrgen Teich |
| 2008 | PPSN | A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. | Martin Lukasiewycz, Michael Gla, Jrgen Teich |
| 2008 | RSP | Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. | Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jrgen Teich |
| 2008 | SAFECOMP | Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. | Michael Gla, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jrgen Teich |
| 2007 | CEC | SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2007 | DATE | Interactive presentation: Reliability-aware system synthesis. | Michael Gla, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jrgen Teich |
| 2007 | EMO | Symbolic Archive Representation for a Fast Nondominance Test. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2007 | FDL | Mapping Actor-Oriented Models to TLM Architectures. | Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jrgen Teich |
| 2007 | FPGA | Efficient hardware checkpointing: concepts, overhead analysis, and implementation. | Dirk Koch, Christian Haubelt, Jrgen Teich |
| 2007 | ISCAS | Modeling and Synthesis of Hardware-Software Morphing. | Dirk Koch, Christian Haubelt, Thilo Streichert, Jrgen Teich |
| 2007 | SAT | Solving Multi-objective Pseudo-Boolean Problems. | Martin Lukasiewycz, Michael Gla, Christian Haubelt, Jrgen Teich |
| 2007 | SCOPES | Efficient event-driven simulation of parallel processor architectures. | Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jrgen Teich |
| 2006 | DATE | Task-accurate performance modeling in SystemC for real-time multi-processor architectures. | Martin Streubhr, Joachim Falk, Christian Haubelt, Jrgen Teich, Rainer Dorsch, Thomas Schlipf |
| 2006 | EuroPar | Topic 18: Embedded Parallel Systems. | Jrgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztin Flautner |
| 2006 | FDL | Efficient Representation and Simulation of Model-Based Designs. | Joachim Falk, Christian Haubelt, Jrgen Teich |
| 2006 | FPL | Minimizing Communication Cost for Reconfigurable Slot Modules. | Sndor P. Fekete, Jan van der Veen, Mateusz Majer, Jrgen Teich |
| 2006 | FPL | Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. | Daniel Ziener, Stefan Assmus, Jrgen Teich |
| 2006 | ICASSP | Modeling and Analysis of Windowed Synchronous Algorithms. | Joachim Keinert, Christian Haubelt, Jrgen Teich |
| 2005 | ASPDAC | A system-level approach to hardware reconfigurable systems. | Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jrgen Teich |
| 2005 | ASPDAC | Online hardware/software partitioning in networked embedded systems. | Thilo Streichert, Christian Haubelt, Jrgen Teich |
| 2005 | CEC | Modeling and analysis of indirect communication in particle swarm optimization. | S. Helwig, Christian Haubelt, Jrgen Teich |
| 2005 | DATE | Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. | Thilo Streichert, Christian Haubelt, Jrgen Teich |
| 2005 | EMO | Initial Population Construction for Convergence Improvement of MOEAs. | Christian Haubelt, Jrgen Gamenik, Jrgen Teich |
| 2005 | FCCM | The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. | Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, Andr Linarth, Jrgen Teich, Sndor P. Fekete, Jan van der Veen |
| 2005 | FPL | DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. | Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jrgen Teich, Sndor P. Fekete, Jan van der Veen |
| 2005 | GECCO | Improving EA-based design space exploration by utilizing symbolic feasibility tests. | Thomas Schlichter, Christian Haubelt, Jrgen Teich |
| 2005 | GI | SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. | Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jrgen Teich, Lothar Thiele |
| 2005 | RSP | A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. | Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jrgen Teich, Sndor P. Fekete, Jan van der Veen |
| 2004 | CEC | Molecular force field parametrization using multi-objective evolutionary algorithms. | Sanaz Mostaghim, Michael Hoffmann, Peter H. Konig, Thomas Frauenheim, Jrgen Teich |
| 2004 | CEC | Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization. | Sanaz Mostaghim, Jrgen Teich |
| 2004 | FPL | Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. | Ali Ahmadinia, Christophe Bobda, Sndor P. Fekete, Jrgen Teich, Jan van der Veen |
| 2004 | FPL | A Dynamic NoC Approach for Communication in Reconfigurable Devices. | Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jrgen Teich |
| 2004 | GECCO | Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. | Neal K. Bambha, Shuvra S. Bhattacharyya, Jrgen Teich, Eckart Zitzler |
| 2004 | ICASSP | Regular mapping for coarse-grained reconfigurable architectures. | Frank Hannig, Hritam Dutta, Jrgen Teich |
| 2003 | ASPDAC | Accelerating design space exploration using pareto-front arithmetics. | Christian Haubelt, Jrgen Teich |
| 2003 | CEC | The role of ε-dominance in multi objective particle swarm optimization methods. | Sanaz Mostaghim, Jrgen Teich |
| 2003 | CEC | Synthesizing passive networks by applying genetic programming and evolution strategies. | Christian Reinhold, P. Kralicek, Werner John, Jrgen Teich |
| 2003 | DATE | Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. | Jens Gerling, Oliver Stbbe, Jrgen Schrage, Gerd Mrozynski, Jrgen Teich |
| 2003 | DATE | SAT-Based Techniques in System Synthesis. | Christian Haubelt, Jrgen Teich, Rainer Feldmann, Burkhard Monien |
| 2003 | EMO | Solving Hierarchical Optimization Problems Using MOEAs. | Christian Haubelt, Sanaz Mostaghim, Jrgen Teich, Ambrish Tyagi |
| 2003 | EMO | Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. | Oliver Schtze, Sanaz Mostaghim, Michael Dellnitz, Jrgen Teich |
| 2003 | FPL | Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. | Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jrgen Teich |
| 2003 | ISCAS | FPGA designs of parallel high performance GF(2 | Cornelia Grabbe, Marcus Bednara, Jrgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi |
| 2002 | CASES | Efficient architecture/compiler co-exploration for ASIPs. | Dirk Fischer, Jrgen Teich, Michael Thies, Ralph Weper |
| 2002 | CEC | Comparison of data structures for storing Pareto-sets in MOEAs. | Sanaz Mostaghim, Jrgen Teich, Ambrish Tyagi |
| 2002 | DATE | System Design for Flexibility. | Christian Haubelt, Jrgen Teich, Kai Richter, Rolf Ernst |
| 2002 | DATE | (Self-)reconfigurable Finite State Machines: Theory and Implementation. | Jrgen Teich, Markus Kster |
| 2002 | ISCAS | Tradeoff analysis of FPGA based elliptic curve cryptography. | Marcus Bednara, M. Daldrup, Jrgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi |
| 2002 | SPAA | Energy estimation of nested loop programs. | Frank Hannig, Jrgen Teich |
| 2001 | CASES | Design space characterization for architecture/compiler co-exploration. | Dirk Fischer, Jrgen Teich, Ralph Weper, Uwe Kastens, Michael Thies |
| 2001 | DATE | Optimal FPGA module placement with temporal precedence constraints. | Sndor P. Fekete, Ekkehard Khler, Jrgen Teich |
| 2001 | EMO | Pareto-Front Exploration with Uncertain Objectives. | Jrgen Teich |
| 2001 | PACT | Design Space Exploration for Massively Parallel Processor Arrays. | Frank Hannig, Jrgen Teich |
| 2001 | WADS | Higher-Dimensional Packing with Order Constraints. | Sndor P. Fekete, Ekkehard Khler, Jrgen Teich |
| 2000 | CASES | A joined architecture/compiler design environment for ASIPs. | Jrgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert |
| 2000 | CEC | Optimizing the efficiency of parameterized local search within global search: a preliminary study. | Eckart Zitzler, Jrgen Teich, Shuvra S. Bhattacharyya |
| 1999 | DAC | Representation of Function Variants for Embedded System Optimization and Synthesis. | Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jrgen Teich |
| 1999 | ICCAD | FunState - an internal design representation for codesign. | Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jrgen Teich |
| 1999 | PDPTA | Compile-time Optimization of Dynamic Hardware Reconfigurations. | Jrgen Teich, Sndor P. Fekete, Jrg Schepers |
| 1998 | FPL | Interfacing Hardware and Software. | Michael Eisenring, Jrgen Teich |
| 1998 | ICCAD | Representation of process mode correlation for scheduling. | Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jrgen Teich, Lothar Thiele |
| 1998 | PPSN | Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. | Jrgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya |