Kazumi Hatayama
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
29
Venues
8
Active years
1989–2023
Best venue rank
National
Where they publish
Papers
29 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | ITC | Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. | Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi |
| 2022 | VTS | Innovative Practices Track: Innovative Analog Circuit Testing Technologies. | Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragn, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa |
| 2021 | IOLTS | Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. | Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi |
| 2021 | ITC | Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. | Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi |
| 2021 | ITC | Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. | Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi |
| 2020 | VTS | Innovative Test Practices in Asia. | Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama |
| 2019 | VTS | Innovative Test Practices in Japan. | Yusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi |
| 2018 | VTS | Innovative practices on test in Japan. | Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama |
| 2017 | VTS | Innovative practices session 9B innovative practices in Asia-1: From quality perspective. | Kazumi Hatayama, Masahiro Ishida |
| 2017 | VTS | Innovative practices session 10B innovative practices in Asia-2: From cost perspective. | Kazumi Hatayama, Masahiro Ishida |
| 2014 | FPGA | Memory block based scan-BIST architecture for application-dependent FPGA testing. | Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue |
| 2013 | VTS | Special session 4B: Elevator talks. | Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia |
| 2012 | ITC | DART: Dependable VLSI test architecture and its implementation. | Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura |
| 2012 | ITC | A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. | Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue |
| 2010 | ISCAS | Scan based process parameter estimation through path-delay inequalities. | Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato |
| 2010 | VTS | Path clustering for adaptive test. | Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato |
| 2009 | ICCAD | A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. | Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara |
| 2009 | VTS | Small Delay Fault Model for Intra-Gate Resistive Open Defects. | Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo |
| 2008 | ETS | A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. | Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja |
| 2008 | ICCAD | Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. | Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara |
| 2007 | ICCAD | Estimation of delay test quality and its application to test generation. | Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo |
| 2006 | VTS | Session Abstract. | Kazumi Hatayama |
| 2004 | ASPDAC | Opportunities with the open architecture test system. | Kazumi Hatayama, Rochit Rajsuman |
| 2003 | ASPDAC | DFT timing design methodology for at-speed BIST. | Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto |
| 2002 | ITC | Application of High-Quality Built-In Test to Industrial Designs. | Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo |
| 1999 | ITC | Low overhead test point insertion for scan-based BIST. | Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada |
| 1997 | VTS | A practical approach to instruction-based test generation for functional modules of VLSI processors. | Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada |
| 1992 | ITC | Sequential Test Generation Based on Real-Value Logic. | Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi |
| 1989 | ITC | Enhanced Delay Test Generator for High-Speed Logic LSIs. | Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama |