| 2010 | ETS | Current-based testable design of level shifters in liquid crystal display drivers. | Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita |
| 2006 | VTS | A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita |
| 2005 | ITC | Low-capture-power test generation for scan-based at-speed testing. | Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2005 | VTS | On Low-Capture-Power Test Generation for Scan Testing. | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2004 | ICCAD | On per-test fault diagnosis using the X-fault model. | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2003 | VLSID | Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. | Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa |
| 2002 | ITC | On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. | Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita |
| 2000 | ASPDAC | Fault models and test generation for IDDQ testing: embedded tutorial. | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
| 2000 | ITC | Precise test generation for resistive bridging faults of CMOS combinational circuits. | Toshiyuki Maeda, Kozo Kinoshita |
| 2000 | VLSID | Test Transformation to Improve Compaction by Statistical Encoding. | Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ETS | Compaction of IDDQ test sequence using reassignment method. | Toshiyuki Maeda, Kozo Kinoshita |
| 1999 | VLSID | Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. | Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita |
| 1998 | VTS | Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. | Hiroyuki Yotsuyanagi, Kozo Kinoshita |
| 1997 | DATE | Design of partially parallel scan chain. | Yoshinobu Higami, Kozo Kinoshita |
| 1997 | VLSID | A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. | Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | VTS | Resynthesis for sequential circuits designed with a specified initial state. | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita |
| 1994 | ISCAS | A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. | Yukiya Miura, Sachio Naito, Kozo Kinoshita |
| 1994 | ITC | Reduced Scan Shift: A New Testing Method for Sequential Circuit. | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita |
| 1994 | VTS | On compacting test sets by addition and removal of test vectors. | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy |
| 1993 | DAC | Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy |
| 1993 | ICCAD | Test generation for multiple faults based on parallel vector pair analysis. | Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita |
| 1992 | ITC | Circuit Design for Built-in Current Testing. | Yukiya Miura, Kozo Kinoshita |
| 1992 | ITC | Testable Designs of Sequential Circuits Under Highly Observable Condition. | Xiaoqing Wen, Kozo Kinoshita |
| 1990 | ITC | On the evaluation of process-fault tolerance ability of CMOS integrated circuits. | Etienne Sicard, Kozo Kinoshita |
| 1990 | ITC | A testable design of logic circuits under highly observable condition. | Xiaoqing Wen, Kozo Kinoshita |
| 1989 | ITC | Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. | Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita |
| 1986 | ITC | Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. | Noriyoshi Itazaki, Kozo Kinoshita |
| 1985 | ITC | A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. | Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita |
| 1984 | ITC | Built-in Testing of Memory Using On-chip Compact Testing Scheme. | Kozo Kinoshita, Kewal K. Saluja |
| 1983 | DAC | Test generation for scan design circuits with tri-state modules and bidirectional terminals. | Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara |
| 1983 | ITC | Design of High-Level Test Language for Digital LSI. | Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita |
| 1981 | DAC | An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. | Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita |
| 1978 | DAC | LORES - Logic Reorganization System. | Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita |