| 2023 | PQCrypto | A High-Performance Hardware Implementation of the LESS Digital Signature Scheme. | Luke Beckwith, Robert Wallace, Kamyar Mohajerani, Kris Gaj |
| 2021 | DATE | Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process. | Kamyar Mohajerani, Richard Haeussler, Rishub Nagpal, Farnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj |
| 2021 | INDOCRYPT | A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks. | Abubakr Abdulgadir, Kamyar Mohajerani, Viet Ba Dang, Jens-Peter Kaps, Kris Gaj |
| 2021 | PQCrypto | Fast NEON-Based Multiplication for Lattice-Based NIST Post-quantum Cryptography Finalists. | Duc Tri Nguyen, Kris Gaj |
| 2020 | CCS | Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks. | Javad Bahrami, Viet Ba Dang, Abubakr Abdulgadir, Khaled N. Khasawneh, Jens-Peter Kaps, Kris Gaj |
| 2020 | DATE | Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography. | Michael X. Lyons, Kris Gaj |
| 2020 | ICA3PP | A Multiplatform Parallel Approach for Lattice Sieving Algorithms. | Michal Andrzejczak, Kris Gaj |
| 2020 | VTS | Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. | Jiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin |
| 2019 | FPL | Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies. | Farnoud Farahmand, Duc Tri Nguyen, Viet Ba Dang, Ahmed Ferozpuri, Kris Gaj |
| 2019 | PQCrypto | Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign. | Farnoud Farahmand, Viet Ba Dang, Duc Tri Nguyen, Kris Gaj |
| 2019 | RAID | COMA: Communication and Obfuscation Management Architecture. | Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan |
| 2018 | CCS | Fixing the CLOC with Fine-grain Leakage Analysis. | William Diehl, Farnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj |
| 2018 | FCCM | Improved Lightweight Implementations of CAESAR Authenticated Ciphers. | Farnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj |
| 2018 | IOLTS | Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes. | Shervin Roshanisefat, Harshith K. Thirumala, Kris Gaj, Houman Homayoun, Avesta Sasan |
| 2017 | DSD | Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates. | Sanjay Deshpande, Kris Gaj |
| 2017 | FPL | Comparison of hardware and software implementations of selected lightweight block ciphers. | William Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj |
| 2016 | DAC | Hybrid STT-CMOS designs for reverse-engineering prevention. | Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Kris Gaj, Houman Homayoun |
| 2016 | DSD | RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two. | William Diehl, Kris Gaj |
| 2016 | DSD | Implementation of a Boolean Masking Scheme for the SCREAM Cipher. | William Diehl, Kris Gaj |
| 2016 | FCCM | High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two. | William Diehl, Kris Gaj |
| 2016 | FPL | Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. | Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski |
| 2016 | INDOCRYPT | AEZ: Anything-But EaZy in Hardware. | Ekawat Homsirikamol, Kris Gaj |
| 2014 | CHES | ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption. | Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wjcik |
| 2014 | FPL | A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. | Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj |
| 2013 | DSD | FPGA PUF Based on Programmable LUT Delays. | Bilal Habib, Kris Gaj, Jens-Peter Kaps |
| 2012 | DSD | A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grstl. | Marcin Rogawski, Kris Gaj |
| 2012 | INDOCRYPT | A Novel Permutation-Based Hash Mode of Operation FP and the Hash Function SAMOSA. | Souradyuti Paul, Ekawat Homsirikamol, Kris Gaj |
| 2011 | CHES | Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. | Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj |
| 2011 | DSD | Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract). | Kris Gaj |
| 2011 | DSD | A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs. | Xin Xin, Jens-Peter Kaps, Kris Gaj |
| 2010 | CHES | Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. | Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski |
| 2010 | FPL | ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. | Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster |
| 2008 | PKC | An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
| 2006 | CHES | Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware. | Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi |
| 2006 | SC | M03 - Reconfigurable supercomputing. | Tarek A. El-Ghazawi, Duncan A. Buell, Volodymyr V. Kindratenko, Kris Gaj |
| 2005 | FPGA | Reconfigurable computers: an empirical analysis (abstract only). | Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha |
| 2005 | FPGA | Image processing library for reconfigurable computers (abstract only). | Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj |
| 2005 | FPL | High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer. | Allen Michalski, Kris Gaj, Duncan A. Buell |
| 2004 | CHES | Efficient Linear Array for Multiplication in GF(2 | Soonhak Kwon, Kris Gaj, Chang Hoon Kim, Chun Pyo Hong |
| 2004 | FPGA | Implementation of elliptic curve cryptosystems over GF(2 | Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi |
| 2004 | FPGA | An embedded true random number generator for FPGAs. | Paul Kohlbrenner, Kris Gaj |
| 2004 | FPL | Implementation of Elliptic Curve Cryptosystems over GF(2 | Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi |
| 2003 | CHES | Very Compact FPGA Implementation of the AES Algorithm. | Pawel Chodowiec, Kris Gaj |
| 2003 | EuroCrypt | Facts and Myths of Enigma: Breaking Stereotypes. | Kris Gaj, Arkadiusz Orlowski |
| 2003 | FPL | IPsec-Protected Transport of HDTV over IP. | Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj |
| 2003 | FPL | An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. | Allen Michalski, Kris Gaj, Tarek A. El-Ghazawi |
| 2001 | FPGA | Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. | Pawel Chodowiec, Po Khuon, Kris Gaj |