| 2026 | ISCAS | A Fully Digital Dynamic Vision Sensor based on Time to First Spike Encoding. | Ayoub Talbi, Ali Naimi, Xavier Lesage, Marco Passy, Skandar Basrour, Laurent Fesquet |
| 2025 | DDECS | Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. | Claire Fenouillet-Branger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudouin Martineau, Marie Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet |
| 2025 | DSD | Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF. | Azzadine Thajte, Sami El Amraoui, Paolo Maistri, Rgis Leveugle, Giorgio Di Natale, Laurent Fesquet |
| 2025 | IOLTS | TIMA-PUF: Time Measurement Based Arbiter PUF. | Azzadine Thajte, Laurent Fesquet, Giorgio Di Natale |
| 2023 | DATE | Low-Throughput Event-Based Image Sensors and Processing. | Laurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stphane Mancini, Gilles Sicard |
| 2020 | ITC | At-speed DfT Architecture for Bundled-data Design. | Ricardo Aquino Guazzelli, Laurent Fesquet |
| 2018 | DATE | Non-intrusive testing technique for detection of Trojans in asynchronous circuits. | Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet |
| 2018 | ISCAS | Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. | Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet |
| 2017 | FDL | Towards consistency checking between HDL and UPF descriptions. | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
| 2017 | FDL | A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
| 2017 | ISCAS | Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. | Ali Skaf, Jean Simatic, Laurent Fesquet |
| 2013 | CHES | A Very High Speed True Random Number Generator with Entropy Assessment. | Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert |
| 2012 | DATE | Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. | Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet |
| 2011 | FDL | Does asynchronous technology bring robustness in synchronous circuit monitoring? | Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya |
| 2011 | RSP | An event-driven FIR filter: Design and implementation. | Taha Beyrouthy, Laurent Fesquet |
| 2010 | DDECS | Synthesis of asynchronous monitors for critical electronic systems. | Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet |
| 2010 | ISCAS | Targeting ultra-low power consumption with non-uniform sampling and filtering. | Laurent Fesquet, Gilles Sicard, Brigitte Bidgaray-Fesquet |
| 2009 | FDL | RAT-based formal verification of QDI asynchronous controllers. | Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet |
| 2007 | FDL | Asynchronous online-monitoring of logical and temporal assertions. | Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione |
| 2007 | ICASSP | Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. | Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin |
| 2006 | RSP | Asynchronous Assertion Monitors for multi-Clock Domain System Verification. | Katell Morin-Allory, Laurent Fesquet, Dominique Borrione |
| 2005 | DATE | FPGA Architecture for Multi-Style Asynchronous Logic. | N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin |
| 2005 | FDL | PSL-based online monitoring of digital systems. | D. Borionne, M. Liu, P. Ostier, Laurent Fesquet |
| 2005 | FPL | A Programmable Logic Architecture for Prototyping Clockless Circuits. | Laurent Fesquet, Marc Renaudin |
| 2005 | FPL | GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin |
| 2002 | DATE | High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. | Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana |
| 2002 | FPL | Implementing Asynchronous Circuits on LUT Based FPGAs. | Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland |
| 1999 | EuroPar | Implementing Snoop-Coherence Protocol for Future SMP Architectures. | Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet |