| 2025 | FCCM | Low-Latency FFT/iFFT RTL Implementation for the FALCON Post-Quantum Signature Algorithm. | Alexandre Ortega, Lilian Bossuet, Brice Colombier |
| 2023 | CARDIS | Deep Stacking Ensemble Learning Applied to Profiling Side-Channel Attacks. | Dorian Llavata, Eleonora Cagli, Rmi Eyraud, Vincent Grosso, Lilian Bossuet |
| 2023 | IOLTS | BALoo: First and Efficient Countermeasure Dedicated to Persistent Fault Attacks. | Pierre-Antoine Tissot, Lilian Bossuet, Vincent Grosso |
| 2023 | RSP | Secured-by-design systems-on-chip: a MBSE Approach. | Raphale Milan, Loc Lagadec, Thotime Bollengier, Lilian Bossuet, Ciprian Teodorov |
| 2022 | CARDIS | Self-timed Masking: Implementing Masked S-Boxes Without Registers. | Mateus Simoes, Lilian Bossuet, Nicolas Bruneau, Vincent Grosso, Patrick Haddad, Thomas Sarno |
| 2022 | DSD | SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals. | Gatan Leplus, Olivier Savry, Lilian Bossuet |
| 2021 | CARDIS | Multi-Spot Laser Fault Injection Setup: New Possibilities for Fault Injection Attacks. | Brice Colombier, Paul Grandamme, Julien Vernay, milie Chanavat, Lilian Bossuet, Lucie de Laulani, Bruno Chassagne |
| 2021 | EuroCrypt | Message-Recovery Laser Fault Injection Attack on the Classic McEliece Cryptosystem. | Pierre-Louis Cayrel, Brice Colombier, Vlad-Florin Dragoi, Alexandre Menu, Lilian Bossuet |
| 2020 | DATE | Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator. | Brice Colombier, Nathalie Bochard, Florent Bernard, Lilian Bossuet |
| 2020 | DDECS | Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. | Julie Roux, Vincent Beroulle, Katell Morin-Allory, Rgis Leveugle, Lilian Bossuet, Frdric Czilly, Frdric Berthoz, Gilles Genvrier, Franois Cerisier |
| 2017 | FPL | Complete activation scheme for FPGA-oriented IP cores design protection. | Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer |
| 2016 | FPGA | Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). | Cdric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui |
| 2016 | FPL | A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. | Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet |
| 2015 | FCCM | Functional Locking Modules for Design Protection of Intellectual Property Cores. | Brice Colombier, Lilian Bossuet |
| 2015 | SAC | Identification of embedded control units by state encoding and power consumption analysis. | Edward Jung, Cdric Marchand, Lilian Bossuet |
| 2013 | ISCA | Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. | Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet |
| 2013 | ISCAS | Electromagnetic analysis on ring oscillator-based true random number generators. | Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer |
| 2012 | DSD | An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF. | Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet |
| 2011 | FPL | Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management. | Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Milos Drutarovsk |
| 2008 | ISCAS | A new orthogonal online digital calibration for time-interleaved analog-to-digital converters. | Guillaume Ferr, Maher Jridi, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet |
| 2006 | ETS | A Low Cost Alternative Method for Harmonics Estimation in a BIST Context. | Vincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy |
| 2003 | FPL | Communication Costs Driven Design Space Exploration for Reconfigurable Architectures. | Lilian Bossuet, Guy Gogniat, Jean Luc Philippe |
| 2003 | ISCAS | Fast prototyping of reconfigurable architectures from a C program. | Sbastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet |