| 2026 | ISCAS | Live Demonstration: A self-adapting randomness extractor for a monolithic QRNG. | Andrea Bonzi, Nicola Massari, Luca Parmesan, Fabio Acerbi, Aymane Bouzafour, Marc Renaudin, Leonardo Gasparini |
| 2026 | ISCAS | Design of a compact QRNG in 22nm standard CMOS technology. | Andrea Bonzi, Nicola Massari, Luca Parmesan, Fabio Acerbi, Sonia Mazzucchi, Aymane Bouzafour, Marc Renaudin, Leonardo Gasparini |
| 2013 | DATE | Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. | Alex Yakovlev, Pascal Vivet, Marc Renaudin |
| 2010 | ETS | Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. | Gaetan Canivet, P. Maistn, Rgis Leveugle, Frdric Valette, Jessy Cldire, Marc Renaudin |
| 2010 | IOLTS | Evaluating transient-fault effects on traditional C-element's implementations. | Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis |
| 2009 | IOLTS | Comparing transient-fault effects on synchronous and on asynchronous circuits. | Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis |
| 2009 | ISLPED | A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. | Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard |
| 2009 | VTS | Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. | Gaetan Canivet, Rgis Leveugle, Jessy Cldire, Frdric Valette, Marc Renaudin |
| 2008 | IOLTS | Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. | Gaetan Canivet, Jessy Cldire, Jean Baptiste Ferron, Frdric Valette, Marc Renaudin, Rgis Leveugle |
| 2007 | FDL | Timed Asynchronous Circuits Modeling using SystemC. | Cedric Koch-Hofer, Marc Renaudin |
| 2007 | ICASSP | Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. | Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin |
| 2007 | IOLTS | Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2007 | SECON | The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. | Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurlien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois |
| 2006 | CHES | Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. | G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin |
| 2006 | FDTC | Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. | Yannick Monnet, Marc Renaudin, Rgis Leveugle, Christophe Clavier, Pascal Moitrel |
| 2006 | IOLTS | Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. | Yannick Monnet, Marc Renaudin, Rgis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet |
| 2006 | IOLTS | Asynchronous Design: Fault Robustness and Security Characteristics. | Marc Renaudin, Yannick Monnet |
| 2005 | DAC | Asynchronous circuits transient faults sensitivity evaluation. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2005 | DATE | DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. | G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain |
| 2005 | DATE | FPGA Architecture for Multi-Style Asynchronous Logic. | N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin |
| 2005 | FPL | A Programmable Logic Architecture for Prototyping Clockless Circuits. | Laurent Fesquet, Marc Renaudin |
| 2005 | FPL | GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin |
| 2005 | IOLTS | Hardening Techniques against Transient Faults for Asynchronous Circuits. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2005 | ISLPED | A 120nm low power asynchronous ADC. | Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric Andr, Marc Renaudin |
| 2004 | DATE | High Security Smartcards. | Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain |
| 2004 | IOLTS | Asynchronous Circuits Sensitivity to Fault Injection. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2002 | DATE | High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. | Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana |
| 2002 | FPL | Implementing Asynchronous Circuits on LUT Based FPGAs. | Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland |
| 2001 | DATE | Low-power systems on chips (SOCs). | Christian Piguet, Marc Renaudin, Thierry J.-F. Omns |
| 1996 | DATE | Asynchronous SRT Dividers: The Real Cost. | Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin |
| 1996 | VLSID | Self timed division and square-root extraction. | Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering |
| 1995 | ISCAS | A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. | Gilles Privat, Frdric Robin, Marc Renaudin, Bachar El-Hassan |
| 1994 | ISCAS | The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. | Marc Renaudin, Bachar El-Hassan |
| 1993 | ICASSP | A general time domain approach for the design of perfect reconstruction modulated filter banks. | Michel Poize, Marc Renaudin, Patrick Venier |
| 1989 | ICCD | Motion estimation VLSI architecture for image coding. | Gilles Privat, Marc Renaudin |