Skip to content

Mateo Valero

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

190

Venues

38

Active years

1983–2026

Best venue rank

A*

Where they publish

Papers

190 indexed papers, newest first.

YearVenueTitleAuthors
2026ISPASSUPSORT: Design and Analysis of Processing-in-Memory Sorting Algorithms using UPMEM.Ivn Vargas Vadivieso, Julian Pavon, Carlos Rojas, Javier Chavez Rubio, Marco A. Ramrez, Luis Villa, Mateo Valero, Osman S. Unsal, Adrin Cristal
2024ISCAQUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.Julian Pavon, Ivn Vargas Valdivieso, Carlos Rojas, Csar Hernndez, Mehmet Aslan, Roger Figueras, Yichao Yuan, Jol Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrin Cristal
2023HPCAVAQUERO: A Scratchpad-based Vector Accelerator for Query Processing.Julin Pavn, Ivn Vargas Valdivieso, Joan Marimon, Roger Figueras, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrin Cristal
2021EuroParPrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy.Vladimir Dimic, Miquel Moret, Marc Casas, Mateo Valero
2021HPCAVIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.Julian Pavon, Ivn Vargas Valdivieso, Adrin Barredo, Joan Marimon, Miquel Moret, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrin Cristal
2020HPCAImproving Predication Efficiency through Compaction/Restoration of SIMD Instructions.Adrin Barredo, Juan M. Cebrian, Miquel Moret, Marc Casas, Mateo Valero
2020ICCSImproving Accuracy and Speeding Up Document Image Classification Through Parallel Systems.Javier Ferrando, Juan Luis Domnguez, Jordi Torres, Ral Garca, David Garca, Daniel Garrido, Jordi Cortada, Mateo Valero
2020ICSRICH: implementing reductions in the cache hierarchy.Vladimir Dimic, Miquel Moret, Marc Casas, Jan Ciesko, Mateo Valero
2020SCRuntime-guided ECC protection using online estimation of memory vulnerability.Luc Jaulmes, Miquel Moret, Mateo Valero, Mattan Erez, Marc Casas
2019IOLTSA Vulnerability Factor for ECC-protected Memory.Luc Jaulmes, Miquel Moret, Mateo Valero, Marc Casas
2019ICSOptimizing computation-communication overlap in asynchronous task-based programs.Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moret, Martin Schulz, Ramn Beivide, Mateo Valero, Abhinav Bhatele
2019ICSPower efficient job scheduling by predicting the impact of processor manufacturing variability.Dimitrios Chasapis, Miquel Moret, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas
2019PPoPPOptimizing computation-communication overlap in asynchronous task-based programs: poster.Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moret, Martin Schulz, Ramn Beivide, Mateo Valero, Abhinav Bhatele
2018HPCAArchitectural Support for Task Dependence Management with Flexible Software Scheduling.Emilio Castillo, Lluc Alvarez, Miquel Moret, Marc Casas, Enrique Vallejo, Jos Luis Bosque, Ramn Beivide, Mateo Valero
2018ICSRuntime-Guided Management of Stacked DRAM Memories in Task Parallel Programs.Lluc Alvarez, Marc Casas, Jess Labarta, Eduard Ayguad, Mateo Valero, Miquel Moret
2018ICSReducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies.Isaac Snchez Barrera, Miquel Moret, Eduard Ayguad, Jess Labarta, Mateo Valero, Marc Casas
2018PPoPPGraph partitioning applied to DAG scheduling to reduce NUMA effects.Isaac Snchez Barrera, Marc Casas, Miquel Moret, Eduard Ayguad, Jess Labarta, Mateo Valero
2018SCRuntime-assisted cache coherence deactivation in task parallel programs.Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moret, Marc Casas
2017EuroParRuntime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals.Vladimir Dimic, Miquel Moret, Marc Casas, Mateo Valero
2017EuroParTo Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy.Esteban Stafford, Borja Prez, Jos Luis Bosque, Ramn Beivide, Mateo Valero
2017EuroSysDirect Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC.Llus Vilanova, Marc Jord, Nacho Navarro, Yoav Etsion, Mateo Valero
2017MASCOTSiQ: An Efficient and Flexible Queue-Based Simulation Framework.Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moret, Mateo Valero, Mario Nemirovsky
2017SBAC-PADSEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems.Qixiao Liu, Miquel Moret, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2016ISCAFuture Vector Microprocessor Extensions for Data Aggregations.Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Mateo Valero
2016ICSRuntime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes.Dimitrios Chasapis, Marc Casas, Miquel Moret, Martin Schulz, Eduard Ayguad, Jess Labarta, Mateo Valero
2016ISLPEDA Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrin Cristal, Mateo Valero
2016ISPASSPerformance analysis of a hardware accelerator of dependence management for task-based dataflow programming models.Xubin Tan, Jaume Bosch, Daniel Jimnez-Gonzlez, Carlos lvarez-Martnez, Eduard Ayguad, Mateo Valero
2016PPoPPRuntime aware architectures.Mateo Valero
2016SCMUSA: a multi-level simulation approach for next-generation HPC machines.Thomas Grass, Csar Allande, Adri Armejach, Alejandro Rico, Eduard Ayguad, Jess Labarta, Mateo Valero, Marc Casas, Miquel Moret
2016SCThe mont-blanc prototype: an alternative approach for HPC systems.Nikola Rajovic, Alejandro Rico, Filippo Mantovani, Daniel Ruiz, Josep Oriol Vilarrubi, Constantino Gmez, Luna Backes, Diego Nieto, Harald Servat, Xavier Martorell, Jess Labarta, Eduard Ayguad, Chris Adeniyi-Jones, Said Derradji, Herv Gloaguen, Piero Lanucara, Nico Sanna, Jean-Franois Mhaut, Kevin Pouget, Brice Videau, Eric Boyer, Momme Allalen, Axel Auweter, David Brayford, Daniele Tafani, Volker Weinberg, Dirk Brmmel, Ren Halver, Jan H. Meinke, Ramn Beivide, Mariano Benito, Enrique Vallejo, Mateo Valero, Alex Ramrez
2015CLUSTERThroughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns.Pablo Fuentes, Enrique Vallejo, Cristobal Camarero, Ramn Beivide, Mateo Valero
2015EuroParRuntime-Aware Architectures.Marc Casas, Miquel Moret, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Jess Labarta, Mateo Valero
2015EuroParHardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core.Nikola Markovic, Daniel Nemirovsky, Veljko Milutinovic, Osman S. Unsal, Mateo Valero, Adrin Cristal
2015HPCAVSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors.Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Mateo Valero
2015HPCAIncreasing multicore system efficiency through intelligent bandwidth shifting.Vctor Jimnez, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell, Francisco J. Cazorla, Mateo Valero
2015ISCACoherence protocol for transparent management of scratchpad memories in shared memory manycore architectures.Lluc Alvarez, Llus Vilanova, Miquel Moret, Marc Casas, Marc Gonzlez, Xavier Martorell, Nacho Navarro, Eduard Ayguad, Mateo Valero
2015ICSCriticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures.Kallia Chronaki, Alejandro Rico, Rosa M. Badia, Eduard Ayguad, Jess Labarta, Mateo Valero
2015SCExploiting asynchrony from exact forward recovery for DUE in iterative solvers.Luc Jaulmes, Marc Casas, Miquel Moret, Eduard Ayguad, Jess Labarta, Mateo Valero
2015SBAC-PADPerformance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs.Nikola Markovic, Daniel Nemirovsky, Osman S. Unsal, Mateo Valero, Adrin Cristal
2014DATEEVX: Vector execution on low power EDGE cores.Milovan Duric, Oscar Palomar, Aaron Smith, Osman S. Unsal, Adrin Cristal, Mateo Valero, Doug Burger
2014EuroParDReAM: Per-Task DRAM Energy Metering in Multicore Systems.Qixiao Liu, Miquel Moret, Jaume Abella, Francisco J. Cazorla, Mateo Valero
2014FPGAAPMC: advanced pattern based memory controller (abstract only).Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Mateo Valero, Santhosh Kumar Rethinagiri
2014FPLMAPC: Memory access pattern based controller.Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Mateo Valero
2014ISCAEnabling preemptive multiprogramming on GPUs.Ivan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramrez, Nacho Navarro, Mateo Valero
2014ISCACODOMs: Protecting software with Code-centric memory Domains.Llus Vilanova, Muli Ben-Yehuda, Nacho Navarro, Yoav Etsion, Mateo Valero
2014ICSAuthor retrospective for software trace cache.Alex Ramrez, Ayose Falcn, Oliverio J. Santana, Mateo Valero
2014SBAC-PADDeTrans: Deterministic and Parallel execution of Transactions.Vesna Smiljkovic, Srdan Stipic, Christof Fetzer, Osman S. Unsal, Adrin Cristal, Mateo Valero
2013DACAPPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation.Bojan Maric, Jaume Abella, Mateo Valero
2013DATEEfficient cache architectures for reliable hybrid voltage operation using EDC codes.Bojan Maric, Jaume Abella, Mateo Valero
2013DSDThe TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.Marco Solinas, Rosa M. Badia, Franois Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Lujn, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stphane Zuckerman, Roberto Giorgi
2013HOTIOFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management.Marina Garca, Enrique Vallejo, Ramn Beivide, Mateo Valero, Germn Rodrguez
2013ICCSEcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory.Sasa Tomic, Ege Akpinar, Adrin Cristal, Osman S. Unsal, Mateo Valero
2013ICPPEfficient Routing Mechanisms for Dragonfly Networks.Marina Garca, Enrique Vallejo, Ramn Beivide, Miguel Odriozola, Mateo Valero
2013ISPASSTrace filtering of multithreaded applications for CMP memory simulation.Alejandro Rico, Alex Ramrez, Mateo Valero
2013PDPIdentifying Critical Code Sections in Dataflow Programming Models.Vladimir Subotic, Jos Carlos Sancho, Jess Labarta, Mateo Valero
2013SCSupercomputing with commodity CPUs: are mobile SoCs ready for HPC?Nikola Rajovic, Paul M. Carpenter, Isaac Gelado, Nikola Puzovic, Alex Ramrez, Mateo Valero
2012ASPLOSOptimal task assignment in multithreaded processors: a statistical approach.Petar Radojkovic, Vladimir Cakarevic, Miquel Moret, Javier Verd, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2012DATETagTM - accelerating STMs with hardware tags for fast meta-data access.Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrin Cristal, Osman S. nsal, Mateo Valero
2012ICPPOn-the-Fly Adaptive Routing in High-Radix Hierarchical Networks.Marina Garca, Enrique Vallejo, Ramn Beivide, Miguel Odriozola, Cristobal Camarero, Mateo Valero, Germn Rodrguez, Jess Labarta, Cyriel Minkenberg
2012ICSEnhancing the performance of assisted execution runtime systems through hardware/software techniques.Gokcen Kestor, Roberto Gioiosa, Osman S. Unsal, Adrin Cristal, Mateo Valero
2012MICROImproving Cache Management Policies Using Dynamic Reuse Distances.Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum
2012MICROVector Extensions for Decision Support DBMS Acceleration.Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Mateo Valero
2012SBAC-PADEfficient Sorting on the Tilera Manycore Architecture.Alessandro Morari, Antonino Tumeo, Oreste Villa, Simone Secchi, Mateo Valero
2012SBAC-PADThe Network Adapter: The Missing Link between MPI Applications and Network Performance.Germn Rodrguez, Cyriel Minkenberg, Ronald P. Luijten, Ramn Beivide, Patrick Geoffray, Jess Labarta, Mateo Valero, Steve Poole
2011EuroParQuantifying the Potential Task-Based Dataflow Parallelism in MPI Applications.Vladimir Subotic, Roger Ferrer, Jos Carlos Sancho, Jess Labarta, Mateo Valero
2011FCCMTMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.Nehir Snmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrin Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
2011ICCDFIMSIM: A fault injection infrastructure for microarchitectural simulators.Gulay Yalcin, Osman S. Unsal, Adrin Cristal, Mateo Valero
2011IOLTSRVC-based time-predictable faulty caches for safety-critical systems.Jaume Abella, Eduardo Quiones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides
2011ISPASSTrace-driven simulation of multithreaded applications.Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramrez, Mateo Valero
2011MASCOTSAn Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.Ruken Zilan, Javier Verd, Jorge Garca-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero
2011PDPThe Impact of Application's Micro-Imbalance on the Communication-Computation Overlap.Vladimir Subotic, Jos Carlos Sancho, Jess Labarta, Mateo Valero
2011RTASIA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems.Marco Paolieri, Eduardo Quiones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero
2011SBAC-PADRapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing.Sasa Tomic, Adrin Cristal, Osman S. nsal, Mateo Valero
2010CISISScalability Analysis of Progressive Alignment on a Multicore.Sebastin Isaza, Friman Snchez, Georgi Gaydadjiev, Alex Ramrez, Mateo Valero
2010CLUSTERDesigning OS for HPC Applications: Scheduling.Roberto Gioiosa, Sally A. McKee, Mateo Valero
2010CLUSTERA Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications.Vladimir Subotic, Jos Carlos Sancho, Jess Labarta, Mateo Valero
2010EuroParLong DNA Sequence Comparison on Multicore Architectures.Friman Snchez, Felipe Cabarcas, Alex Ramrez, Mateo Valero
2010ICSOverlapping communication and computation by using a hybrid MPI/SMPSs approach.Vladimir Marjanovic, Jess Labarta, Eduard Ayguad, Mateo Valero
2010ISPASSSimulation environment for studying overlap of communication and computation.Vladimir Subotic, Jess Labarta, Mateo Valero
2010MICROTask Superscalar: An Out-of-Order Task Pipeline.Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramrez, Rosa M. Badia, Eduard Ayguad, Jess Labarta, Mateo Valero
2010MICROArchitectural Support for Fair Reader-Writer Locking.Enrique Vallejo, Ramn Beivide, Adrin Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero
2010PPoPPEffective communication and computation overlap with hybrid MPI/SMPSs.Vladimir Marjanovic, Jess Labarta, Eduard Ayguad, Mateo Valero
2010PPoPPThread to strand binding of parallel network applications in massive multi-threaded systems.Petar Radojkovic, Vladimir Cakarevic, Javier Verd, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2010PPoPPDebugging programs that use atomic blocks and transactional memory.Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrin Cristal, Mateo Valero
2009CLUSTEROblivious routing schemes in extended generalized Fat Tree networks.Germn Rodrguez, Cyriel Minkenberg, Ramn Beivide, Ronald P. Luijten, Jess Labarta, Mateo Valero
2009HPCCDynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory.Sutirtha Sanyal, Sourav Roy, Adrin Cristal, Osman S. Unsal, Mateo Valero
2009ICPADSScalability of Macroblock-level Parallelism for H.264 Decoding.Mauricio Alvarez-Mesa, Alex Ramrez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero
2009ICPPCode Semantic-Aware Runahead Threads.Tanaus Ramrez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2009ISCAHardware support for WCET analysis of hard real-time multicore systems.Marco Paolieri, Eduardo Quiones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009ICSQuakeTM: parallelizing a complex sequential application using transactional memory.Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Tim Harris, Mateo Valero
2009ICSExploring pattern-aware routing in generalized fat tree networks.Germn Rodrguez, Ramn Beivide, Cyriel Minkenberg, Jess Labarta, Mateo Valero
2009ICSA european perspective on supercomputing.Mateo Valero
2009MICROCharacterizing the resource-sharing levels in the UltraSPARC T2 processor.Vladimir Cakarevic, Petar Radojkovic, Javier Verd, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2009MICROEazyHTM: eager-lazy hardware transactional memory.Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adri Armejach, Adrin Cristal, Osman S. Unsal, Tim Harris, Mateo Valero
2009PPoPPTurbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.Chinmay Eishan Kulkarni, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Mateo Valero
2009PPoPPAtomic quake: using transactional memory in an interactive multiplayer game server.Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Tim Harris, Mateo Valero
2009SBAC-PADThread to Core Assignment in SMT On-Chip Multiprocessors.Carmelo Acosta, Francisco J. Cazorla, Alex Ramrez, Mateo Valero
2008CECEvolutionary system for prediction and optimization of hardware architecture performance.Pedro ngel Castillo Valdivieso, Juan Julin Merelo Guervs, Miquel Moret, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jimnez Laredo, Sally A. McKee
2008HPCARunahead Threads to improve SMT performance.Tanaus Ramrez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2008ICPPMFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.Carmelo Acosta, Francisco J. Cazorla, Alex Ramrez, Mateo Valero
2008ISCASoftware-Controlled Priority Characterization of POWER5 Processor.Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero
2008ISCAA Two-Level Load/Store Queue Based on Execution Locality.Miquel Perics, Adrin Cristal, Francisco J. Cazorla, Rubn Gonzlez, Alexander V. Veidenbaum, Daniel A. Jimnez, Mateo Valero
2008MICROA distributed processor state management architecture for large-window processors.Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramrez, Adrin Cristal, Mateo Valero
2008SCA dynamic scheduler for balancing HPC applications.Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero
2008SBAC-PADSelection of the Register File Size and the Resource Allocation Policy on SMT Processors.Jess Alastruey, Teresa Monreal, Francisco J. Cazorla, Vctor Vials, Mateo Valero
2008SBAC-PADMeasuring Operating System Overhead on CMT Processors.Petar Radojkovic, Vladimir Cakarevic, Javier Verd, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero
2007EuroParHardware Transactional Memory with Operating System Support, HTMOS.Sasa Tomic, Adrin Cristal, Osman S. Unsal, Mateo Valero
2007ISPASSPerformance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.Mauricio Alvarez, Esther Salam, Alex Ramrez, Mateo Valero
2006HPCAA decoupled KILO-instruction processor.Miquel Perics, Adrin Cristal, Rubn Gonzlez, Daniel A. Jimnez, Mateo Valero
2005CASESArchitectural support for real-time task scheduling in SMT processors.Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernndez, Alex Ramrez, Mateo Valero
2005ICCDA New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.Marco Antonio Ramrez, Adrin Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2005ICPPA Complexity-Effective Simultaneous Multithreading Architecture.Carmelo Acosta, Ayose Falcn, Alex Ramrez, Mateo Valero
2005ICPPA Vector-SIMD-VLIW Architecture for Multimedia Applications.Esther Salam, Mateo Valero
2005ICSAn asymmetric clustered processor based on value content.Rubn Gonzlez, Adrin Cristal, Miquel Perics, Mateo Valero, Alexander V. Veidenbaum
2005ISPASSPerformance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering.Raimir Holanda, Javier Verd, Jorge Garca-Vidal, Mateo Valero
2005ISPASSOn the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications.Friman Snchez, Mauricio Alvarez, Esther Salam, Alex Ramrez, Mateo Valero
2004DSDImplicit vs. Explicit Resource Allocation in SMT Processors.Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernndez, Alex Ramrez, Mateo Valero
2004EuroParFeasibility of QoS for SMT.Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernndez, Alex Ramrez, Mateo Valero
2004EuroParMaintaining Thousands of In-flight Instructions.Adrin Cristal, Oliverio J. Santana, Mateo Valero
2004HPCAOut-of-Order Commit Processors.Adrin Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
2004HPCAA Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors.Ayose Falcn, Alex Ramrez, Mateo Valero
2004ISCAProphet/Critic Hybrid Branch Prediction.Ayose Falcn, Jared Stark, Alex Ramrez, Konrad Lai, Mateo Valero
2004ISCAA Content Aware Integer Register File Organization.Rubn Gonzlez, Adrin Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
2004MICRODynamically Controlled Resource Allocation in SMT Processors.Francisco J. Cazorla, Alex Ramrez, Mateo Valero, Enrique Fernndez
2003GLOBECOMA conflict-free memory banking architecture for fast VOQ packet buffers.Jorge Garcia, Lloren Cerd, Jess Corbal, Mateo Valero
2003ICSDynamic memory instruction bypassing.Daniel Ortega, Eduard Ayguad, Mateo Valero
2003ISPASSAn MPEG-4 performance study for non-SIMD, general purpose architectures.Sally A. McKee, Zhen Fang, Mateo Valero
2003MICRODesign and Implementation of High-Performance Memory Systems for Future Packet Buffers.Jorge Garca-Vidal, Jess Corbal, Lloren Cerd, Mateo Valero
2002CASESCost effective memory disambiguation for multimedia codes.Esther Salam, Jess Corbal, Carlos lvarez, Mateo Valero
2002EuroParA Comparative Study of Redundancy in Trace Caches (Research Note).Hans Vandierendonck, Alex Ramrez, Koenraad De Bosschere, Mateo Valero
2002ICPPHardware Schemes for Early Register Release.Teresa Monreal, Vctor Vials, Antonio Gonzlez, Mateo Valero
2002ISCASpeculative Dynamic Vectorization.Alex Pajuelo, Antonio Gonzlez, Mateo Valero
2002MICROThree-dimensional memory vectorization for high bandwidth media memory systems.Jess Corbal, Roger Espasa, Mateo Valero
2002MICROFetching instruction streams.Alex Ramrez, Oliverio J. Santana, Josep Llus Larriba-Pey, Mateo Valero
2001EuroParBranch Prediction Using Profile Data.Alex Ramrez, Josep Llus Larriba-Pey, Mateo Valero
2001EuroParTopic 15+20: Multimedia and Embedded Systems.Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
2001HPCADLP + TLP Processors for the Next Generation of Media Workloads.Jess Corbal, Roger Espasa, Mateo Valero
2001ISCACode layout optimizations for transaction processing workloads.Alex Ramrez, Luiz Andr Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep Llus Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
2001ICSOn the potential of tolerant region reuse for multimedia applications.Carlos lvarez, Jess Corbal, Esther Salam, Mateo Valero
2001ICSA novel renaming mechanism that boosts software prefetching.Daniel Ortega, Mateo Valero, Eduard Ayguad
2001MICROModulo scheduling with integrated register spilling for clustered VLIW architectures.Javier Zalamea, Josep Llosa, Eduard Ayguad, Mateo Valero
2001SPAAA cost effective architecture for vectorizable numerical and multimedia applications.Francisca Quintana, Jess Corbal, Roger Espasa, Mateo Valero
2000EuroParParallel Computer Architecture.Silvia M. Mller, Per Stenstrm, Mateo Valero, Stamatis Vassiliadis
2000EuroParOn the Performance of Fetch Engines Running DSS Workloads.Carlos Navarro, Alex Ramrez, Josep Llus Larriba-Pey, Mateo Valero
2000HPCATrace Cache Redundancy: Red & Blue Traces.Alex Ramrez, Josep Llus Larriba-Pey, Mateo Valero
2000ISCAMultiple-banked register file architectures.Jos-Lorenzo Cruz, Antonio Gonzlez, Mateo Valero, Nigel P. Topham
2000MICROTwo-level hierarchical register file organization for VLIW processors.Javier Zalamea, Josep Llosa, Eduard Ayguad, Mateo Valero
2000PLDIImproved spill code generation for software pipelined loops.Javier Zalamea, Josep Llosa, Eduard Ayguad, Mateo Valero
1999EuroParInstruction-Level Parallelism and Uniprocessor Architecture - Introduction.Pascal Sainrat, Mateo Valero
1999ICPPImpact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures.David Lpez, Josep Llosa, Eduard Ayguad, Mateo Valero
1999ICPPOptimization of Instruction Fetch for Decision Support Workloads.Alex Ramrez, Josep Llus Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
1999ICSIncreasing effective IPC by exploiting distant parallelism.Ivan Martel, Daniel Ortega, Eduard Ayguad, Mateo Valero
1999ICSAdding a vector unit to a superscalar processor.Francisca Quintana, Jess Corbal, Roger Espasa, Mateo Valero
1999ICSSoftware trace cache.Alex Ramrez, Josep Llus Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
1999MICROExploiting a New Level of DLP in Multimedia Applications.Jess Corbal, Roger Espasa, Mateo Valero
1999MICRODelaying Physical Register Allocation through Virtual-Physical Registers.Teresa Monreal, Antonio Gonzlez, Mateo Valero, Jos Gonzlez, Vctor Vials
1999SCMOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications.Jess Corbal, Roger Espasa, Mateo Valero
1998HPCAVirtual-Physical Registers.Antonio Gonzlez, Jos Gonzlez, Mateo Valero
1998ICSVector Architectures: Past, Present and Future.Roger Espasa, Mateo Valero, James E. Smith
1998ICSResource Widening Versus Replication: Limits and Performance-cost Trade-off.David Lpez, Josep Llosa, Mateo Valero, Eduard Ayguad
1998ICSA Performance Study of Out-of-order Vector Architectures and Short Registers.Luis Villa, Roger Espasa, Mateo Valero
1998MICROWidening Resources: A Cost-effective Technique for Aggressive ILP Architectures.David Lpez, Josep Llosa, Mateo Valero, Eduard Ayguad
1998PDPA case for merging the ILP and DLP paradigms.Francisca Quintana, Roger Espasa, Mateo Valero
1998PDPEffective usage of vector registers in decoupled vector architectures.Luis Villa, Roger Espasa, Mateo Valero
1997HiPCSimultaneous multithreaded vector architecture: merging ILP and DLP for high performance.Roger Espasa, Mateo Valero
1997HiPCVirtual registers.Antonio Gonzlez, Mateo Valero, Jos Gonzlez, Teresa Monreal Arnal
1997HPCAMultithreaded Vector Architectures.Roger Espasa, Mateo Valero
1997ICSA Victim Cache for Vector Registers.Roger Espasa, Mateo Valero
1997ICSEliminating Cache Conflict Misses through XOR-Based Placement Functions.Antonio Gonzlez, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
1997ICSIncreasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs.David Lpez, Mateo Valero, Josep Llosa, Eduard Ayguad
1997MICROOut-of-Order Vector Architectures.Roger Espasa, Mateo Valero, James E. Smith
1996HPCADecoupled Vector Architectures.Roger Espasa, Mateo Valero
1996MICROHeuristics for Register-Constrained Software Pipelining.Josep Llosa, Mateo Valero, Eduard Ayguad
1996PDPLoop Parallelization: Revisiting Framework of Unimodular Transformations.Jordi Torres, Eduard Ayguad, Jess Labarta, Mateo Valero
1995HPCANon-Consistent Dual Register Files to Reduce Register Pressure.Josep Llosa, Mateo Valero, Eduard Ayguad
1995ISCAVector Multiprocessors with Arbitrated Memory Access.Montse Peiron, Mateo Valero, Eduard Ayguad, Toms Lang
1995ICSA Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality.Antonio Gonzlez, Carlos Aliagas, Mateo Valero
1995MICROHypernode reduction modulo scheduling.Josep Llosa, Mateo Valero, Eduard Ayguad, Antonio Gonzlez
1995PDPQuantitative analysis of vector code.Roger Espasa, Mateo Valero, David A. Padua, Marta Jimnez, Eduard Ayguad
1994ICSSynchronized access to streams in SIMD vector multiprocessors.Montse Peiron, Mateo Valero, Eduard Ayguad
1994PDPAccess To Vectors In Multi-module Memories.Mateo Valero, Montse Peiron, Eduard Ayguad
1993PDPAccess to streams in multiprocessor systems.Mateo Valero, Montse Peiron, Eduard Ayguad
1992ISCAIncreasing the Number of Strides for Conflict-Free Vector Access.Mateo Valero, Toms Lang, Jos M. Llabera, Montse Peiron, Eduard Ayguad, Juan J. Navarro
1992ICSConflict-free access of vectors with power-of-two strides.Mateo Valero, Toms Lang, Eduard Ayguad
1991CCCMapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units.Miguel Valero-Garca, Juan J. Navarro, Jos J. M. Liabera, Mateo Valero, Toms Lang
1989ISCASystematic Hardware Adaptation of Systolic Algorithms.Miguel Valero-Garca, Juan J. Navarro, Jos M. Llabera, Mateo Valero
1986ICPPSolving Matrix Problems with No Size Restriction on a Systolic Array Processor.Juan J. Navarro, Jos M. Llabera, Mateo Valero
1986ISCAComputing Size-Independent Matrix Problems on Systolic Array Processors.Juan J. Navarro, Jos M. Llabera, Mateo Valero
1985ISCAAnalysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering.Jos M. Llabera, Mateo Valero, Enrique Herrada Lillo, Jess Labarta
1983SIGMETRICSA performance evaluation of the multiple bus network for multiprocessor systems.Mateo Valero, Jos Mara Llabera, Jess Labarta, Emilio Sanvicente, Toms Lang