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Michael Hbner

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

58

Venues

18

Active years

2004–2022

Best venue rank

A*

Where they publish

Papers

58 indexed papers, newest first.

YearVenueTitleAuthors
2022DATEHealth Monitoring of Milling Tools under Distinct Operating Conditions by a Deep Convolutional Neural Network model.Priscile Suawa Fogou, Michael Hbner
2021DATEArtificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy.Florian Fricke, Safdar Mahmood, Javier Hoffmann, Marcelo Brandalero, Sascha Liehr, Simon Kern, Klas Meyer, Stefan Kowarik, Stephan Westerdick, Michael Maiwald, Michael Hbner
2021DDECSDesign and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation.Mitko Veleski, Michael Hbner, Milos Krstic, Rolf Kraemer
2021DSDTowards Machine Learning Support for Embedded System Tests.Stefan Scharoba, Kai-Uwe Basener, Jens Bielefeldt, Hans-Werner Wiesbrock, Michael Hbner
2021FPLAITIA: Embedded AI Techniques for Industrial Applications.Marcelo Brandalero, Mitko Veleski, Hector Gerardo Muoz Hernandez, Muhammad Ali, Laurens Le Jeune, Toon Goedem, Nele Mentens, Jurgen Vandendriessche, Lancelot Lhoest, Bruno da Silva, Abdellah Touhafi, Diana Goehringer, Michael Hbner
2021FPLAccelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures.Keyvan Shahin, Michael Hbner
2021FPLThe SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservices.Angelos S. Voros, Christos Panagiotou, Stavros Zogas, Georgios Keramidas, Christos P. Antonopoulos, Michael Hbner, Nikolaos S. Voros
2021GIEinsatz von Deep Learning fr den Test Eingebetteter Systeme.Jens Bielefeldt, Kai-Uwe Basener, Siddique Reza Khan, Mozhdeh Massah, Hans-Werner Wiesbrock, Stefan Scharoba, Michael Hbner
2021IOLTSTowards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework.Mitko Veleski, Michael Hbner, Milos Krstic, Rolf Kraemer
2021MICROPerformance analysis of application-specific instruction-set routers in networks-on-chip.Jens Rettkowski, Julian Haase, Sven Primus, Michael Hbner, Diana Ghringer
2020COMPSACDeep Learning Utilization in Beamforming Enhancement for Medical Ultrasound.Mariam M. Fouad, Yousef Metwally, Georg Schmitz, Michael Hbner, Mohamed A. Abd El Ghany
2020DACProactive Aging Mitigation in CGRAs through Utilization-Aware Allocation.Marcelo Brandalero, Bernardo Neuhaus Lignati, Antonio Carlos Schneider Beck, Muhammad Shafique, Michael Hbner
2020DATERESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendrfer, Christian Sauer, Anton Klotz, Michael Hbner, Jrg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2020DSDHighly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip.Mitko Veleski, Michael Hbner, Milos Krstic, Rolf Kraemer
2020FPLMCEA: A Resource-Aware Multicore CGRA Architecture for the Edge.Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hbner, Mateus Beck Rutzig, Antonio Carlos Schneider Beck
2020IOLTSReduced-Precision DWC for Mixed-Precision GPUs.Fernando Fernandes dos Santos, Marcelo Brandalero, Pedro Martins Basso, Michael Hbner, Luigi Carro, Paolo Rech
2017DATEAn open reconfigurable research platform as stepping stone to exascale high-performance computing.Dirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios N. Pnevmatikatos, Michael Hbner, Tobias Becker, Alex J. W. Thom
2017FPLA dynamic partial reconfigurable overlay concept for PYNQ.Benedikt Janen, Pascal Zimprich, Michael Hbner
2017GIHardware Accelerator Framework Approach for Dynamic Partial Reconfigurable Overlays on Xilinx PYNQ.Benedikt Janen, Tim Wingender, Michael Hbner
2016DATEComputation and communication challenges to deploy robots in assisted living environments.Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Ghringer, Michael Hbner, Stasinos Konstantopoulos, Theodoros Giannakopoulos, Vangelis Karkaletsis, Vaggelis Mariatos
2016DSDAutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs.Andr Lalevee, Pierre-Henri Horrein, Matthieu Arzel, Michael Hbner, Sandrine Vaton
2016FPGAFGPU: An SIMT-Architecture for FPGAs.Muhammed Al Kadi, Benedikt Janen, Michael Hbner
2015ETFAThe value of FPGAs as reconfigurable hardware enabling Cyber-Physical Systems.Toms Grimm, Benedikt Janen, Osvaldo Navarro, Michael Hbner
2015EUCA Framework to the Design and Programming of Many-Core Focal-Plane Vision Processors.Jones Yudi Mori, Carlos H. Llanos, Michael Hbner
2015EUCA Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Ghringer, Michael Hbner, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros
2014FPLMulti-FPGA reconfigurable system for accelerating MATLAB simulations.Muhammed Al Kadi, Max Ferger, Volker Stegemann, Michael Hbner
2014ISPAFuture Trends on Adaptive Processing Systems.Benedikt Janen, Jones Yudi Mori, Osvaldo Navarro, Diana Ghringer, Michael Hbner
2013DSDStopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hbner, Jean-Philippe Diguet
2013ISCASOptimizations for an efficient reconfiguration of an ASIP-based turbo decoder.Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hbner
2012ASPDACInvasive manycore architectures.Jrg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hbner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
2012DATEVirtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.Stephan Werner, Oliver Oey, Diana Ghringer, Michael Hbner, Jrgen Becker
2012DSDFrom Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.Jrgen Becker, Timo Stripf, Oliver Oey, Michael Hbner, Steven Derrien, Daniel Mnard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Ghringer
2011DATEFast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.Joachim Meyer, Juanjo Noguera, Michael Hbner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jrgen Becker
2011FPLRAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.Diana Ghringer, Stephan Werner, Michael Hbner, Jrgen Becker
2011FPLEmbedded Systems Start-Up under Timing Constraints on Modern FPGAs.Joachim Meyer, Juanjo Noguera, Michael Hbner, Rodney Stewart, Jrgen Becker
2011ISCASA FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker.Matthias Rmmele-Werner, Thomas Perschke, Lars Braun, Michael Hbner, Jrgen Becker
2010EuroParHigh Performance Architectures and Compilers.Pedro C. Diniz, Marco Danelutto, Denis Barthou, Marc Gonzales, Michael Hbner
2010FCCMA Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.Diana Ghringer, Michael Hbner, Michael Benz, Jrgen Becker
2010FPGAA semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).Diana Ghringer, Michael Hbner, Michael Benz, Jrgen Becker
2010FPLReconfigurable Hardware for Power-over-Fiber Applications.Michael Dreschmann, Michael Hbner, Moritz Rger, Oliver Sander, Christos Klamouris, Jrgen Becker, Wolfgang Freude, Juerg Leuthold
2010ICCCNNetwork Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems.Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hbner, Jrgen Teich
2009FPLDynamic reconfigurable mixed-signal architecture for safety critical applications.Romuald Girardey, Michael Hbner, Jrgen Becker
2009FPLStar-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.Diana Ghringer, Bin Liu, Michael Hbner, Jrgen Becker
2008DATEDesign Flows, Communication Based Design and Architectures in Automotive Electronic Systems.Jrgen Becker, Michael Hbner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer
2008DATEDesign of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Khnle, Florian Ries, Michael Hbner, Jrgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco
2008DATECost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.Katarina Paulsson, Michael Hbner, Jrgen Becker
2008FPLFine grain reconfigurable architectures.Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008FPLData path driven waveform-like reconfiguration.Lars Braun, Katarina Paulsson, Herrmann Krmer, Michael Hbner, Jrgen Becker
2008FPLA multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hbner, Jrgen Becker
2008FPLNew dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.Diana Ghringer, Michael Hbner, Thomas Perschke, Jrgen Becker
2008FPLExploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.Katarina Paulsson, Michael Hbner, Jrgen Becker
2007FPLCircuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.Lars Braun, Michael Hbner, Jrgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007FPLA Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures.Philipp Graf, Michael Hbner, Klaus D. Mller-Glaser, Jrgen Becker
2007FPLImplementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.Katarina Paulsson, Michael Hbner, Gnther Auer, Michael Dreschmann, Jrgen Becker
2007FPLOn-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the THER Project.Katarina Paulsson, Michael Hbner, Jrgen Becker, Jean-Marc Philippe, Christian Gamrat
2004FPLPartial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.Brandon Blodget, Christophe Bobda, Michael Hbner, Adronis Niyonkuru
2004FPLScalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.Michael Hbner, Michael Ullmann, Lars Braun, A. Klausmann, Jrgen Becker
2004FPLOn-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.Michael Ullmann, Michael Hbner, Bjrn Grimm, Jrgen Becker