Naifeng Jing
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
68
Venues
19
Active years
2011–2026
Best venue rank
A*
Where they publish
Papers
68 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPDAC | Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. | Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2026 | ASPLOS | AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection. | Houshu He, Naifeng Jing, Li Jiang, Xiaoyao Liang, Zhuoran Song |
| 2026 | ISCA | CHIME: A Case for Efficient Long-Context Attention-FC Disaggregated Inference with DIMM-PIM. | Qingyuan Liu, Liyan Chen, Haocheng Wang, Yanning Yang, Dong Du, Zhigang Mao, Naifeng Jing, Yubin Xia, Haibo Chen |
| 2025 | ASPDAC | MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. | Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | DAC | AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory. | Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | DAC | MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization. | Chunyu Qi, Xuhang Wang, Ruiyang Chen, Yuanzheng Yao, Naifeng Jing, Chen Zhang, Jun Wang, Zhihui Fu, Xiaoyao Liang, Zhuoran Song |
| 2025 | DAC | Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator. | Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing |
| 2025 | DAC | SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPU. | Yuanzheng Yao, Chen Zhang, Chunyu Qi, Ruiyang Chen, Jun Wang, Zhihui Fu, Naifeng Jing, Xiaoyao Liang, Zhuoran Song |
| 2025 | DATE | HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. | Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2025 | HPCA | AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. | Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2025 | ICCD | RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V. | Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang |
| 2025 | ISCA | LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference. | Zhiwen Mo, Lei Wang, Jianyu Wei, Zhichen Zeng, Shijie Cao, Lingxiao Ma, Naifeng Jing, Ting Cao, Jilong Xue, Fan Yang, Mao Yang |
| 2025 | MICRO | HEAT: NPU-NDP HEterogeneous Architecture for Transformer-Empowered Graph Neural Networks. | Ruiyang Chen, Zhuoran Song, Yicheng Zheng, Zeyu Zhu, Gang Li, Naifeng Jing, Xiaoyao Liang, Haibing Guan |
| 2024 | ASPDAC | Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. | Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2024 | ASPDAC | SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. | Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2024 | ASPLOS | CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing. | Zhuoran Song, Chunyu Qi, Fangxin Liu, Naifeng Jing, Xiaoyao Liang |
| 2024 | DAC | Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. | Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing |
| 2024 | EuroPar | Watt: A Write-Optimized RRAM-Based Accelerator for Attention. | Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, Xiaoyao Liang |
| 2024 | ICCD | Early: An Importance-Aware Early Firing and Exit for SNN Acceleration. | Xuan Zhang, Zhuoran Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang |
| 2024 | ISCA | UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space. | Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2024 | ISCAS | A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. | Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang |
| 2024 | ISCAS | A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. | Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing |
| 2023 | ASPDAC | An Efficient near-Bank Processing Architecture for Personalized Recommendation System. | Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng |
| 2023 | DAC | AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity. | Xiaolong Lin, Gang Li, Zizhao Liu, Yadong Liu, Fan Zhang, Zhuoran Song, Naifeng Jing, Xiaoyao Liang |
| 2023 | DATE | PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. | Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang |
| 2023 | FPL | Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. | Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing |
| 2023 | ICCD | ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. | Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang |
| 2023 | ICCD | HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model. | Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang |
| 2022 | ASPDAC | Boosting ReRAM-based DNN by Row Activation Oversubscription. | Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing |
| 2022 | DAC | EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. | Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2022 | DAC | E | Zhuoran Song, Zhongkai Yu, Naifeng Jing, Xiaoyao Liang |
| 2022 | ICCAD | Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy. | Xing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang |
| 2022 | ICCD | GCNTrain: A Unified and Efficient Accelerator for Graph Convolutional Neural Network Training. | Heng Lu, Zhuoran Song, Xing Li, Naifeng Jing, Xiaoyao Liang |
| 2022 | MICRO | Ristretto: An Atomized Processing Architecture for Sparsity-Condensed Stream Flow in CNN. | Gang Li, Weixiang Xu, Zhuoran Song, Naifeng Jing, Jian Cheng, Xiaoyao Liang |
| 2021 | DATE | Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. | Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing |
| 2021 | ISCAS | Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. | Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing |
| 2021 | ISPA | PIPArch: Programmable Image Processing Architecture Using Sliding Array. | Feiyang Wu, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, Xiaoyao Liang |
| 2020 | AIME | A High-Throughput Tumor Location System with Deep Learning for Colorectal Cancer Histopathology Image. | Jing Ke, Yiqing Shen, Yi Guo, Jason D. Wright, Naifeng Jing, Xiaoyao Liang |
| 2020 | DAC | GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. | Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing |
| 2020 | FPL | A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. | Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang |
| 2020 | HPCC | PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural Network Acceleration. | Zhaoming Jiang, Zhuoran Song, Xiaoyao Liang, Naifeng Jing |
| 2020 | ISCA | DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration. | Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, Xiaoyao Liang |
| 2020 | ISCAS | Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. | Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing |
| 2020 | ISCAS | A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. | Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou |
| 2020 | MICRO | VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration. | Zhuoran Song, Feiyang Wu, Xueyuan Liu, Jing Ke, Naifeng Jing, Xiaoyao Liang |
| 2019 | ASPDAC | HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. | Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang |
| 2019 | ASPDAC | A sharing-aware L1.5D cache for data reuse in GPGPUs. | Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing |
| 2019 | ISCAS | A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. | Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing |
| 2018 | FPGA | A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). | Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2018 | ICCAD | AXNet: approximate computing using an end-to-end trainable neural network. | Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang |
| 2018 | ICCAD | Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. | Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2017 | DAC | Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. | Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2017 | DAC | On Quality Trade-off Control for Approximate Computing Using Iterative Training. | Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang |
| 2016 | ICCD | CNFET-based high throughput register file architecture. | Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang |
| 2016 | ISPDC | Applying Victim Cache in High Performance GPGPU Computing. | Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, Naifeng Jing |
| 2016 | MICRO | Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. | Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang |
| 2015 | DAC | Jump test for metallic CNTs in CNFET-based SRAM. | Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang |
| 2015 | ICCAD | Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. | Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao |
| 2015 | ISLPED | Bank stealing for conflict mitigation in GPGPU Register File. | Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang |
| 2015 | ISLPED | CGSharing: Efficient content sharing in GPU-based cloud gaming. | Xiangyu Wu, Yuanfang Xia, Naifeng Jing, Xiaoyao Liang |
| 2015 | ITC | On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. | Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu |
| 2013 | ISCA | An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. | Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang |
| 2013 | ISLPED | Compiler assisted dynamic register file in GPGPU. | Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang |
| 2011 | FPGA | Fault modeling and characteristics of SRAM-based FPGAs (abstract only). | Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He |
| 2011 | FPL | IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. | Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He |
| 2011 | FPL | Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. | Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He |
| 2011 | ICCAD | Mitigating FPGA interconnect soft errors by in-place LUT inversion. | Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He |
| 2011 | ISCAS | A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. | Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao |