| 2025 | IOLTS | Anomalous IoT Behavior Detection Based on SARIMA Reference Waveform. | Ryusei Eda, Nozomu Togawa |
| 2025 | QCE | Constraint Coefficient Tuning of Spin-Variable Reduction for QAP. | Raio Aoki, Tatsuhiko Shirai, Nozomu Togawa |
| 2025 | QCE | QUBO Simplification Method for Improving Solution Convergence Speed Using an Ising Machine. | Shinnosuke Inaba, Takeru Ota, Chihiro Dogo, Kazuhiro Saito, Nozomu Togawa |
| 2025 | QCE | SubQUBO Construction Based on Grid Reduction Method Using an Ising Machine. | Koki Mita, Takeru Ota, Nozomu Togawa |
| 2025 | QCE | Qubit-Width-Aware Grover Adaptive Search for Combinatorial Optimization Problems. | Takuto Moriya, Masashi Tawada, Nozomu Togawa |
| 2025 | QCE | Evaluating pVSQA for Large-Sized Constrained Optimization on Quantum Simulator. | Takeru Ota, Tatsuhiko Shirai, Mikio Morita, Koichi Kimura, Yutaka Takita, Nozomu Togawa |
| 2025 | VTC | Enriching Experiences Through Shared Moments: Travel Recommendation for Heterogeneous Users Using Ising Machines. | Siya Bao, Nozomu Togawa |
| 2024 | IOLTS | Anomalous IoT Behavior Detection by Generated Power Waveforms with Hyper-parameter Tuning. | Ryusei Eda, Kota Hisafuru, Nozomu Togawa |
| 2024 | QCE | Optimization of Base Station Power Supply Selection by Quantum Annealing. | Chihiro Dogo, Kazuhiro Saito, Nozomu Togawa |
| 2024 | QCE | Large-Sized VQE Performance Profiling in Quantum Chemistry Using a Multi-Node Quantum Simulator. | Keisuke Fukada, Tatsuhiko Shirai, Mikio Morita, Yoshinori Tomita, Koichi Kimura, Nozomu Togawa |
| 2024 | QCE | Non-zero Coefficients Removing Method to Improve the Ising Machine Solving Performance. | Kinya Iwata, Masashi Tawada, Nozomu Togawa |
| 2024 | QCE | Multi-Day Intermodal Trip Planning Using subQUBO Annealing with Correction Processing. | Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa |
| 2024 | QCE | Personalized Course Selection Optimization Using an Ising Machine. | Takeru Ota, Keisuke Fukada, Nozomu Togawa |
| 2024 | QCE | Variable Reduction Method for Quadratic Three-Dimensional Assignment Problem with FMQA. | Sora Tomita, Tatsuhiko Shirai, Nozomu Togawa |
| 2024 | QCE | QUBO Coefficient Dynamic Ratio Shrinking Method for Quantum Annealers. | Yuta Yachi, Masashi Tawada, Nozomu Togawa |
| 2023 | TrustCom | Membership Inference Attacks against GNN-based Hardware Trojan Detection. | Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa |
| 2022 | IOLTS | An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes. | Kota Hisafuru, Kazunari Takasaki, Nozomu Togawa |
| 2022 | IOLTS | Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. | Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa |
| 2021 | CANS | Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training. | Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Nozomu Togawa |
| 2021 | IOLTS | Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. | Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa |
| 2021 | IOLTS | Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests. | Tatsuki Kurihara, Nozomu Togawa |
| 2021 | IOLTS | An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM. | Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa |
| 2020 | ASPDAC | FPGA-based Heterogeneous Solver for Three-Dimensional Routing. | Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa |
| 2020 | ASPDAC | Theory of Ising Machines and a Common Software Platform for Ising Machines. | Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa |
| 2020 | IOLTS | Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods. | Tatsuki Kurihara, Kento Hasegawa, Nozomu Togawa |
| 2020 | IOLTS | An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors. | Kazunari Takasaki, Kento Hasegawa, Ryoichi Kida, Nozomu Togawa |
| 2019 | ESORICS | Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. | Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa |
| 2019 | IOLTS | Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis. | Kento Hasegawa, Kiyoshi Chikamatsu, Nozomu Togawa |
| 2019 | IOLTS | Error Correction Coding of Stochastic Numbers Using BER Measurement. | Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2019 | ISCAS | Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. | Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
| 2018 | IOLTS | Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2018 | IOLTS | An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. | Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2018 | ISCAS | A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2018 | TrustCom | Hardware Trojan Detection Utilizing Machine Learning Approaches. | Kento Hasegawa, Youhua Shi, Nozomu Togawa |
| 2017 | IOLTS | Hardware Trojans classification for gate-level netlists using multi-layer neural networks. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2017 | IOLTS | Hardware Trojan detection and classification based on steady state learning. | Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2017 | ISCAS | Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
| 2017 | ISCAS | Effective write-reduction method for MLC non-volatile memory. | Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa |
| 2016 | IOLTS | Hardware Trojans classification for gate-level netlists based on machine learning. | Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2016 | IOLTS | Redesign for untrusted gate-level netlists. | Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
| 2016 | ISCAS | Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. | Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa |
| 2015 | ASPDAC | A bit-write reduction method based on error-correcting codes for non-volatile memories. | Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa |
| 2015 | DATE | A score-based classification method for identifying hardware-trojans at gate-level netlists. | Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2015 | GLOBECOM | Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization. | Kou Kikuta, Eiji Oki, Naoaki Yamanaka, Nozomu Togawa, Hidenori Nakazato |
| 2015 | ICCAD | Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. | Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa |
| 2015 | ISCAS | A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. | Kotaro Terada, Masao Yanagisawa, Nozomu Togawa |
| 2014 | ISCAS | Scan-based attack on the LED block cipher using scan signatures. | Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa |
| 2014 | ISCAS | Linear and bi-linear interpolation circuits using selector logics and their evaluations. | Masashi Shio, Masao Yanagisawa, Nozomu Togawa |
| 2013 | ISCAS | Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. | Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2013 | ISCAS | A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. | Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa |
| 2013 | PRDC | Secure Scan Design with Dynamically Configurable Connection. | Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
| 2012 | ISCAS | An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. | Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa |
| 2012 | ISCAS | A novel BMNoC configuration algorithm utilizing communication volume and locality among cores. | Seungju Lee, Nozomu Togawa, Takashi Aoki, Akira Onozawa |
| 2010 | ASPDAC | Scan-based attack against elliptic curve cryptosystems. | Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | State-dependent changeable scan architecture against scan-based side channel attacks. | Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ASPDAC | Exact and fast L1 cache simulation for embedded systems. | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ITC | Design-for-secure-test for crypto cores. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | GECOM: Test data compression combined with all unknown response masking. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISCAS | Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISLPED | Power-efficient LDPC code decoder architecture. | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2006 | ASPDAC | An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. | Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ISCAS | A parallel LSI architecture for LDPC decoder improving message-passing schedule. | Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2005 | ASPDAC | Reconfigurable adaptive FEC system with interleaving. | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2005 | ASPDAC | A processor core synthesis system in IP-based SoC design. | Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | ICCD | Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. | Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa |
| 2005 | ISCAS | Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. | Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A cosynthesis algorithm for application specific processors with heterogeneous datapaths. | Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | Instruction set and functional unit synthesis for SIMD processor cores. | Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A thread partitioning algorithm in low power high-level synthesis. | Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2003 | ASPDAC | A hardware/software partitioning algorithm for SIMD processor cores. | Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2002 | VLSID | VLSI Architecture for a Flexible Motion Estimation with Parameters. | Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2001 | ASPDAC | Area/delay estimation for digital signal processor cores. | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2000 | ASPDAC | An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). | Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1999 | ASPDAC | A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. | Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. | Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. | Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1997 | ASPDAC | A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1995 | ASPDAC | Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1994 | ICCAD | A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1994 | ISCAS | A Simultaneous Placement and Global Routing Algorithm for FPGAs. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |