| 2026 | AsiaCCS | SCREAM: Secure Channels for Real-time Evaluation of Additive Manufacturing. | Prithwish Basu Roy, Jason Blocklove, Mudit Bhargava, Hammond Pearce, Prashanth Krishnamurthy, Ozgur Sinanoglu, Nikhil Gupta, Farshad Khorrami, Ramesh Karri |
| 2026 | AsiaCCS | POSTER: Hector - An Agentic LLM Framework for Logic Locking. | Prithwish Basu Roy, Akashdeep Saha, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri |
| 2026 | ASPDAC | Benchmarking Continual Learning on Netlists with Circuit-Targeted Graph Neural Networks. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | DATE | Black-Box Robustness Probing of Graph Neural Networks for VLSI Circuit Netlists. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | DATE | Interpretable Graph Neural Networks for Fault Detection in Circuit Netlists. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | DATE | Focus Session: LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs. | Buddhi Perera, Zeng Wang, Weihua Xiao, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel, Ramesh Karri |
| 2026 | DATE | Special Day - GUIDE: GenAI Units In Digital Design Education. | Weihua Xiao, Jason Blocklove, Matthew DeLorenzo, Johann Knechtel, Ozgur Sinanoglu, Kanad Basu, Jeyavijayan Rajendran, Siddharth Garg, Ramesh Karri |
| 2026 | ICISSP | Securing Hyper-Dimensional Computing: A Locking Mechanism with FPGA Implementation. | Rupesh Raj Karn, Paul R. Genssler, Hussam Amrouch, Ozgur Sinanoglu |
| 2026 | ICISSP | LLM-Driven Python-to-Rust Translation for Efficient and Safe Code for Neural Networks: llm4py2rs. | Rupesh Raj Karn, Johann Knechtel, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu |
| 2026 | IOLTS | Structural Security Entropy: A Novel Prior for Robust GNN-Based Security Assessment of Netlists. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | IOLTS | Interpretable GNNs for Fault Detection in Circuits. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | ISCAS | Educational Perspectives on LLM Architectures: Analyzing Code Generation for Circuits and Systems. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | ISCAS | Dynamic GNNs for Continual Learning on Circuits. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2026 | ISCAS | Power Side-Channel Attacks in Nanosheet Circuits. | Mohammed Nabeel, Hadi Nour Eddine, Mahdi Benkhelifa, Ozgur Sinanoglu, Michail Maniatakos, Johann Knechtel, Hussam Amrouch |
| 2026 | VTS | LLM4SecurePQC: LLM-Driven and Side-Channel Resilient Hardware Synthesis of PQC Cores. | Mohammed Nabeel, Buddhi Perera, Zeng Wang, Ozgur Sinanoglu, Johann Knechtel, Ramesh Karri |
| 2026 | VTS | RTL-Forge: CNF-Anchored, LLM-Assisted Verilog Generation. | Prithwish Basu Roy, Akashdeep Saha, Manaar Alam, Johann Knechtel, Michail Maniatakos, Ozgur Sinanoglu, Ramesh Karri |
| 2025 | DATE | RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. | Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam, Ramesh Karri, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel |
| 2025 | ICCD | LLM-Driven Code Generation for Neural Networks on FPGAs: Bridging Python and HLS. | Rupesh Raj Karn, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu |
| 2025 | ICISSP | Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2025 | ISCAS | LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks. | Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel |
| 2025 | ISCAS | Educational Framework for Power Side-Channel Attacks on Neural Networks in Embedded Systems. | Rupesh Raj Karn, Prithwish Basu Roy, Johann Knechtel, Ozgur Sinanoglu |
| 2025 | VTS | GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness. | Akashdeep Saha, Prithwish Basu Roy, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Lilas Alrahis |
| 2024 | DATE | HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition. | Paul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch |
| 2024 | ICCAD | ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. | Jitendra Bhandari, Animesh Basak Chowdhury, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel |
| 2024 | ICMLC | Selective Forgetting in Task-Progressive Learning Through Machine Unlearning. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2024 | IOLTS | Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks. | Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique |
| 2024 | ISCAS | Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. | Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu |
| 2023 | ASPDAC | Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. | Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu |
| 2023 | DAC | ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. | Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan |
| 2023 | DSN | AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. | Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu |
| 2023 | IOLTS | ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules. | Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique |
| 2023 | ISCAS | TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. | Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu |
| 2023 | ISLPED | FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. | Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique |
| 2023 | VTS | Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? | Lilas Alrahis, Ozgur Sinanoglu |
| 2022 | DATE | MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. | Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu |
| 2022 | ICCAD | Embracing Graph Neural Networks for Hardware Security. | Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu |
| 2022 | ICCAD | AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. | Tim Bcher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch |
| 2022 | IJCNN | NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. | Mahya Morid Ahmadi, Lilas Alrahis, Alessio Colucci, Ozgur Sinanoglu, Muhammad Shafique |
| 2021 | DAC | Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. | Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri |
| 2021 | DATE | GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. | Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique, Ozgur Sinanoglu |
| 2021 | DATE | Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques. | Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu |
| 2021 | ICCAD | UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. | Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu |
| 2021 | ICCAD | Security Closure of Physical Layouts ICCAD Special Session Paper. | Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri |
| 2021 | ICCAD | Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. | Jens Lienig, Susann Rothe, Matthias Thiele, Nikhil Rangarajan, Mohammed Ashraf, Mohammed Nabeel, Hussam Amrouch, Ozgur Sinanoglu, Johann Knechtel |
| 2020 | DATE | DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. | Nimisha Limaye, Ozgur Sinanoglu |
| 2020 | ETS | Design Obfuscation versus Test. | Farimah Farahmandi, Ozgur Sinanoglu, Ronald D. Blanton, Samuel Pagliarini |
| 2019 | ASPDAC | ScanSAT: unlocking obfuscated scan chains. | Lilas Alrahis, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu |
| 2019 | DAC | Attacking Split Manufacturing from a Deep Learning Perspective. | Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu |
| 2019 | DATE | MixLock: Securing Mixed-Signal Circuits via Logic Locking. | Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Lourat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos |
| 2019 | DATE | A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. | Abhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu |
| 2019 | ETS | Revisiting Logic Locking for Reversible Computing. | Nimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu |
| 2019 | ICCAD | Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. | Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu |
| 2019 | IOLTS | 3D Integration: Another Dimension Toward Hardware Security. | Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu |
| 2018 | ASPDAC | Concerted wire lifting: Enabling secure and cost-effective split manufacturing. | Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu |
| 2018 | DAC | Raise your game for split manufacturing: restoring the true functionality through BEOL. | Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu |
| 2018 | DATE | Advancing hardware security using polymorphic and stochastic spin-hall effect devices. | Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja |
| 2018 | DATE | Towards provably-secure performance locking. | Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran |
| 2018 | ICCAD | Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. | Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel |
| 2018 | ICCAD | Customized locking of IP blocks on a multi-million-gate SoC. | Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Ozgur Sinanoglu |
| 2018 | ITC | Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition. | Muhammad Yasin, Ozgur Sinanoglu |
| 2018 | VTS | ATPG-based cost-effective, secure logic locking. | Abhrajit Sengupta, Mohammed Thari Nabeel, Muhammad Yasin, Ozgur Sinanoglu |
| 2017 | ASPDAC | Security analysis of Anti-SAT. | Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran |
| 2017 | CCS | Provably-Secure Logic Locking: From Theory To Practice. | Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu |
| 2017 | DAC | On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. | Johann Knechtel, Ozgur Sinanoglu |
| 2017 | ICCAD | Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. | Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu |
| 2017 | ICCAD | Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. | Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu |
| 2016 | DATE | Activation of logic encrypted chips: Pre-test or post-test? | Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu |
| 2016 | ICCAD | CamoPerturb: secure IC camouflaging for minterm protection. | Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran |
| 2016 | IOLTS | Power-side-channel analysis of carbon nanotube FET based design. | Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu |
| 2016 | VTS | Thwarting timing attacks on NEMS relay based designs. | Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu |
| 2015 | ICCD | Security implications of cyberphysical digital microfluidic biochips. | Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri |
| 2015 | IOLTS | Power analysis attacks on ARX: An application to Salsa20. | Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu |
| 2015 | ISCAS | A secure design-for-test infrastructure for lifetime security of SoCs. | Jerry Backer, Sk Subidh Ali, Kurt Rosenfeld, David Hly, Ozgur Sinanoglu, Ramesh Karri |
| 2015 | VTS | TMO: A new class of attack on cipher misusing test infrastructure. | Sk Subidh Ali, Ozgur Sinanoglu |
| 2014 | DAC | Secure Memristor-based Main Memory. | Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu |
| 2014 | DATE | Approximating the age of RF/analog circuits through re-characterization and statistical estimation. | Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri |
| 2014 | ETS | Test-mode-only scan attack using the boundary scan chain. | Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri |
| 2014 | ITC | Test-mode-only scan attack and countermeasure for contemporary scan architectures. | Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri |
| 2014 | VTS | Detection, diagnosis, and repair of faults in memristor-based memories. | Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu |
| 2013 | CCS | Security analysis of integrated circuit camouflaging. | Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | DATE | Is split manufacturing secure? | Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | DATE | Adaptive reduction of the frequency search space for multi-vdd digital circuits. | Chandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu |
| 2013 | ETS | Reconciling the IC test and security dichotomy. | Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, Yiorgos Makris |
| 2013 | ICCD | Sneak path testing and fault modeling for multilevel memristor-based memories. | Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu |
| 2013 | IOLTS | Scan attack in presence of mode-reset countermeasure. | Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | IOLTS | High-level synthesis for security and trust. | Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | ITC | VLSI testing based security metric for IC camouflaging. | Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | VLSID | Sneak-path Testing of Memristor-based Memories. | Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu |
| 2012 | DAC | Security analysis of logic obfuscation. | Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri |
| 2012 | DATE | Logic encryption: A fault analysis perspective. | Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri |
| 2012 | ETS | Toggle-masking scheme for x-filtering. | Abishek Ramdas, Ozgur Sinanoglu |
| 2012 | ETS | DfT support for launch and capture power reduction in launch-off-capture testing. | Samah Mohamed Saeed, Ozgur Sinanoglu |
| 2012 | ETS | Adaptive testing of chips with varying distributions of unknown response bits. | Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev |
| 2012 | ETS | Adaptive testing: Conquering process variations. | Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu, Peter C. Maxwell |
| 2012 | ICCD | Engineering crossbar based emerging memory technologies. | Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu |
| 2012 | IOLTS | Test access mechanism for chips with spare identical cores. | Ozgur Sinanoglu |
| 2012 | VLSID | Eliminating Performance Penalty of Scan. | Ozgur Sinanoglu |
| 2011 | ETS | Toggle-Based Masking Scheme for Clustered Unknown Response Bits. | Ozgur Sinanoglu |
| 2011 | VTS | Revival of partial scan: Test cube analysis driven conversion of flip-flops. | Nader Alawadhi, Ozgur Sinanoglu |
| 2011 | VTS | Design and analysis of ring oscillator based Design-for-Trust technique. | Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri |
| 2011 | VTS | Expedited response compaction for scan power reduction. | Samah Mohamed Saeed, Ozgur Sinanoglu |
| 2010 | ETS | Add-on blocks and algorithms for improving stimulus compression. | Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla |
| 2010 | ETS | Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. | Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu |
| 2010 | IOLTS | Reconfigurable low-power Concurrent Error Detection in logic circuits. | Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu |
| 2010 | ITC | Predictive analysis for projecting test compression levels. | Ozgur Sinanoglu, Sobeeh Almukhaizim |
| 2009 | ITC | X-alignment techniques for improving the observability of response compactors. | Ozgur Sinanoglu, Sobeeh Almukhaizim |
| 2008 | DATE | Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. | Ozgur Sinanoglu, Erik Jan Marinissen |
| 2008 | ITC | Peak Power Reduction Through Dynamic Partitioning of Scan Chains. | Sobeeh Almukhaizim, Ozgur Sinanoglu |
| 2008 | ITC | Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors. | Ozgur Sinanoglu |
| 2007 | DATE | A non-intrusive isolation approach for soft cores. | Ozgur Sinanoglu, Tsvetomir Petrov |
| 2007 | DATE | Diagnosis, modeling and tolerance of scan chain hold-time violations. | Ozgur Sinanoglu, Philip Schremmer |
| 2004 | ASPDAC | Efficient RT-level fault diagnosis methodology. | Ozgur Sinanoglu, Alex Orailoglu |
| 2004 | DATE | Scan Power Minimization through Stimulus and Response Transformations. | Ozgur Sinanoglu, Alex Orailoglu |
| 2004 | ETS | Pipelined test of SOC cores through test data transformations. | Ozgur Sinanoglu, Alex Orailoglu |
| 2004 | ICCD | Extending the Applicability of Parallel-Serial Scan Designs. | Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu |
| 2004 | ITC | Autonomous Yet Deterministic Test of SOC Cores. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | DSD | Hierarchical Constraint Conscious RT-level Test Generation. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | ETS | Parity-based output compaction for core-based SOCs [logic testing]. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | ICCAD | Partial Core Encryption for Performance-Efficient Test of SOCs. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | ICCD | Aggressive Test Power Reduction Through Test Stimuli Transformation. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | ITC | Modeling Scan Chain Modifications For Scan-in Test Power Minimization. | Ozgur Sinanoglu, Alex Orailoglu |
| 2002 | ETS | Dynamic test data transformations for average and peak power reductions. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2002 | ICCAD | A novel scan architecture for power-efficient, rapid test. | Ozgur Sinanoglu, Alex Orailoglu |
| 2002 | ITC | Scan Power Reduction Through Test Data Transition Frequency Analysis. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2002 | VTS | Test Power Reduction through Minimization of Scan Chain Transitions. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2001 | ITC | Space and time compaction schemes for embedded cores. | Ozgur Sinanoglu, Alex Orailoglu |
| 2001 | VTS | RT-level Fault Simulation Based on Symbolic Propagation. | Ozgur Sinanoglu, Alex Orailoglu |